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Estimation of <sup>99</sup> Mo production rates from natural molybdenum in research reactors
Blaauw, M.,Ridikas, D.,Baytelesov, S.,Salas, P. S. Bedregal,Chakrova, Y.,Eun-Ha, Cho,Dahalan, R.,Fortunato, A. H.,Jacimovic, R.,Kling, A.,Muñ,oz, L.,Mohamed, N. M. A.,Pá,rká,nyi, D. Springer Netherlands 2017 Journal of radioanalytical and nuclear chemistry Vol.311 No.1
<P>Molybdenum-99 is one of the most important radionuclides for medical diagnostics. In 2015, the International Atomic Energy Agency organized a round-robin exercise where the participants measured and calculated specific saturation activities achievable for the <SUP>98</SUP>Mo(n,γ)<SUP>99</SUP>Mo reaction. This reaction is of interest as a means to locally, and on a small scale, produce <SUP>99</SUP>Mo from natural molybdenum. The current paper summarises a set of experimental results and reviews the methodology for calculating the corresponding saturation activities. Activation by epithermal neutrons and also epithermal neutron self-shielding are found to be of high importance in this case.</P>
Morrison III, William R,Blaauw, Brett R,Short, Brent D,Nielsen, Anne L,Bergh, James C,Krawczyk, Greg,Park, Yong‐,Lak,Butler, Bryan,Khrimian, Ashot,Leskey, Tracy C John Wiley Sons, Ltd 2019 Pest Management Science Vol.75 No.1
<P><B>Abstract</B></P><P><B>BACKGROUND</B></P><P>Introduction of <I>Halyomorpha halys</I> (Stål) in the USA has disrupted many established integrated pest management programs for specialty crops, especially apple. While current management heavily relies on insecticides, one potential alternative tactic is attract‐and‐kill (AK), whereby large numbers of <I>H. halys</I> are attracted to and retained in a circumscribed area using attractive semiochemicals and removed from the foraging population with an insecticide. The goal of this study was to evaluate if AK implementation in commercial apple orchards can result in levels of <I>H. halys</I> damage that are equal to or less than those from grower standard management programs.</P><P><B>RESULTS</B></P><P>Over 2 years at farms in five Mid‐Atlantic USA states, we found that the use of AK resulted in 2–7 times less damage compared with grower standard plots, depending on year and period. At selected trees on which AK was implemented, over 10,000 <I>H. halys</I> individuals were killed in two growing seasons, and the use of AK reduced the crop area treated with insecticide against <I>H. halys</I> by 97%. Using AK had no impact on the natural enemy or secondary pest community over the same period.</P><P><B>CONCLUSIONS</B></P><P>Overall, the use of AK was effective at managing low to moderate <I>H. halys</I> populations in apple orchards, but must be optimized to increase economic feasibility for grower adoption. © 2018 Society of Chemical Industry</P>
A 42 nJ/Conversion On-Demand State-of-Charge Indicator for Miniature IoT Li-Ion Batteries
Jeong, Junwon,Jeong, Seokhyeon,Sylvester, Dennis,Blaauw, David,Kim, Chulwoo IEEE 2019 IEEE journal of solid-state circuits Vol.54 No.2
<P>An energy-efficient state-of-charge (SOC) indication algorithm and integrated system for low-power wireless sensor nodes with the miniature Internet of Things (IoT) batteries are introduced in this paper. Based on the key findings that the miniature Li-ion batteries exhibit a fast response to the battery current transient, we propose an instantaneous linear extrapolation (ILE) algorithm and circuit system based on the ILE algorithm allowing accurate on-demand estimation of SOC. Due to the on-demand operation, an always-ON current integration is avoided, reducing power and energy consumption by several orders of magnitude. Furthermore, the proposed SOC indicator does not require a battery disconnection from the load, ensuring continuous operation of the applications. The system is implemented in a 180-nm CMOS technology. The power consumption is 42 nW, and maximum SOC indication error is 1.7%. The minimum applicable battery capacity is as low as <TEX>$2~\mu $</TEX>Ah.</P>
Jang, Taekwang,Jeong, Seokhyeon,Jeon, Dongsuk,Choo, Kyojin David,Sylvester, Dennis,Blaauw, David IEEE 2018 IEEE journal of solid-state circuits Vol.53 No.1
<P>Programmability is one of the most significant advantages of a digital phase-locked loop (PLL) compared with a charge-pump PLL. In this paper, a digital PLL that extends programmability to include noise is introduced. A digitally controlled oscillator (DCO) using a switched capacitor for frequency feedback is proposed to maintain a constant figure of merit while reconfiguring its noise performance. The proposed DCO offers an accurate and linear frequency tuning curve that is insensitive to environmental changes. A noise detection circuit using the statistical property of a bang-bang phase and frequency detector is proposed to autonomously adjust the output noise level depending on the noise specification. A prototype design is fabricated in a 28-nm FDSOI process. The integrated phase noise of the proposed PLL can be configured from 2.5 to 15 ps, while the power consumption ranges from 1.7 to 5 mW.</P>
A Wire-overhead-free Reset Propagation Scheme for Millimeter-scale Sensor Systems
Lee, Inhee,Bang, Suyoung,Kim, Yejoong,Kim, Gyouho,Sylvester, Dennis,Blaauw, David,Lee, Yoonmyung The Institute of Electronics and Information Engin 2017 Journal of semiconductor technology and science Vol.17 No.4
This paper presents a novel reset scheme for mm-scale sensing systems with stringent volume and area constraints. In such systems, multi-layer structure is required to maximize the silicon area per volume and minimize the system size. The multi-layer structure requires wirebonding connections for power delivery and communication among layers, but the area overhead for wirebonding pads can be significant. The proposed reset scheme exploits already existing power wires and thus does not require additional wires for system-wide reset operation. To implement the proposed reset scheme, a power management unit is designed to impose reset condition, and a reset detector is designed to interpret the reset condition indicated by the power wires. The reset detector uses a coupling capacitor for the initial power-up and a feedback path to hold the developed supply voltage. The prototype reset detector is fabricated in a $180-{\mu}m$ CMOS process, and the measurement results with the prototype mm-scale system confirmed robust reset operation over a wide range of temperatures and voltages.
A Wire-overhead-free Reset Propagation Scheme for Millimeter-scale Sensor Systems
Inhee Lee,Suyoung Bang,Yejoong Kim,Gyouho Kim,Dennis Sylvester,David Blaauw,Yoonmyung Lee 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.4
This paper presents a novel reset scheme for mm-scale sensing systems with stringent volume and area constraints. In such systems, multi-layer structure is required to maximize the silicon area per volume and minimize the system size. The multi-layer structure requires wirebonding connections for power delivery and communication among layers, but the area overhead for wirebonding pads can be significant. The proposed reset scheme exploits already existing power wires and thus does not require additional wires for system-wide reset operation. To implement the proposed reset scheme, a power management unit is designed to impose reset condition, and a reset detector is designed to interpret the reset condition indicated by the power wires. The reset detector uses a coupling capacitor for the initial power-up and a feedback path to hold the developed supply voltage. The prototype reset detector is fabricated in a 180-μm CMOS process, and the measurement results with the prototype mm-scale system confirmed robust reset operation over a wide range of temperatures and voltages.
A 23-mW Face Recognition Processor with Mostly-Read 5T Memory in 40-nm CMOS
Jeon, Dongsuk,Dong, Qing,Kim, Yejoong,Wang, Xiaolong,Chen, Shuai,Yu, Hao,Blaauw, David,Sylvester, Dennis IEEE 2017 IEEE journal of solid-state circuits Vol.52 No.6
<P>This paper presents an energy-efficient face detection and recognition processor aimed at mobile applications. The algorithmic optimizations including hybrid search scheme for face detection significantly reduce computational complexity and architecture modification such as feature memory segmentation and further reduce energy consumption. We utilize characteristics of the implemented algorithm and propose a 5T SRAM design heavily optimized for mostly-read operations. Systematic reset and write schemes allow for reliable data write operation. The 5T SRAM reduces the cell area by 7.2% compared to a conventional 6T bit cell in logic rule while significantly improving read margin and voltage scalability due to a decoupled read path. The fabricated processor consumes only 23 mW while processing both face detection and recognition in real time at 5.5 frames/s throughput.</P>
MBus: A Fully Synthesizable Low-power Portable Interconnect Bus for Millimeter-scale Sensor Systems
Lee, Inhee,Kuo, Ye-Sheng,Pannuto, Pat,Kim, Gyouho,Foo, Zhiyoong,Kempke, Ben,Jeong, Seokhyeon,Kim, Yejoong,Dutta, Prabal,Blaauw, David,Lee, Yoonmyung The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.6
This paper presents a fully synthesizable low power interconnect bus for millimeter-scale wireless sensor nodes. A segmented ring bus topology minimizes the required chip real estate with low input/output pad count for ultra-small form factors. By avoiding the conventional open drain-based solution, the bus can be fully synthesizable. Low power is achieved by obviating a need for local oscillators in member nodes. Also, aggressive power gating allows low-power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with a power management unit that has nW standby mode. A 3-module system including the bus is fabricated in a 180 nm process. The entire system consumes 8 nW in standby mode, and the bus achieves 17.5 pJ/bit/chip.
Shim, Minseob,Jeong, Seokhyeon,Myers, Paul D.,Bang, Suyoung,Shen, Junhua,Kim, Chulwoo,Sylvester, Dennis,Blaauw, David,Jung, Wanyeong IEEE 2017 IEEE journal of solid-state circuits Vol.52 No.4
<P>This paper presents a new energy-efficient ring oscillator collapse-based comparator, named edge-pursuit comparator (EPC). This comparator automatically adjusts the performance by changing the comparison energy according to its input difference without any control, eliminating unnecessary energy spent on coarse comparisons. Furthermore, a detailed analysis of the EPC in the phase domain shows improved energy efficiency over conventional comparators even without energy scaling, and wider resolution tuning capability with small load capacitance and area. The EPC is used in a successive-approximation-register analog-to-digital converter (SAR ADC) design, which supplements a 10 b differential coarse capacitive digital-to-analog converter (CDAC) with a 5 b common-mode CDAC. This offers an additional 5 b of resolution with common mode to differential gain tuning that improves linearity by reducing the effect of switch parasitic capacitance. A test chip fabricated in 40 nm CMOS shows 74.12 dB signal-to-noise and distortion ratio and 173.4 dB Schreier Figure-of-Merit. With the full ADC consuming 1.17 mu W, the comparator consumes 104 nW, which is only 8.9% of the full ADC power, proving the comparator's energy efficiency.</P>
MBus : A Fully Synthesizable Low-power Portable Interconnect Bus for Millimeter-scale Sensor Systems
Inhee Lee,Ye-Sheng Kuo,Pat Pannuto,Gyouho Kim,Zhiyoong Foo,Ben Kempke,Seokhyeon Jeong,Yejoong Kim,Prabal Dutta,David Blaauw,Yoonmyung Lee 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.6
This paper presents a fully synthesizable low power interconnect bus for millimeter-scale wireless sensor nodes. A segmented ring bus topology minimizes the required chip real estate with low input/output pad count for ultra-small form factors. By avoiding the conventional open drain-based solution, the bus can be fully synthesizable. Low power is achieved by obviating a need for local oscillators in member nodes. Also, aggressive power gating allows low-power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with a power management unit that has nW standby mode. A 3-module system including the bus is fabricated in a 180 nm process. The entire system consumes 8 nW in standby mode, and the bus achieves 17.5 pJ/bit/chip.