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Scalable-Delay-Insensitive Optimization based on Lock Relation
Pitchayapatchaya Srikram,Arthit Thongtak 대한전자공학회 2015 ITC-CSCC :International Technical Conference on Ci Vol.2015 No.6
This paper presents further studies on Scalable-Delay-Insensitive (SDI) optimization, an approach to revise Signal Transition Graph (STG) in order to relieve a restricted and pessimistic delay model for asynchronous control circuit synthesis. This paper extends the new algorithm based on the lock relation which analyze a causal relation to determine the signal transitions to be optimized and their safeness properties in case the STG has multiple tokens of initial marking. The proposed algorithm can be satisfied to properties of STG. Furthermore, it is not only performed to single cycle signal but also to multiple cycle signal STGs. As the results, our method can reduce the overhead from original STG used and implement the circuits which operate correctly.