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1.5차원 색온도 계산 알고리즘의 개발 및 하드웨어 구조 설계
홍두일,변형수,강봉순,홍창희 동아대학교 정보기술연구소 2002 情報技術硏究所論文誌 Vol.10 No.1
In this paper, we propose the development of 1.5-dimensional color-temperature calculation algorithm for easy hardware implementation. In conventional method, we use Robertson algorithm while calculating color-temperature, but this algorithm is hardly implemented by hardware cause the complexity of equations. At this point, we use daylight locus equation for easy hardware implementation and nearly get result of Robertson algorithm, but this result has an error in calculations. Accordingly, we propose the 1.5-dimensional color-temperature calculation algorithm equal the result of Robertson algorithm. To convert from Robertson algorithm with complexity equation to 1.5-dimensional equation for easy hardware implementation, we can implemented color-temperature calculation system by using 1.5-dimensional algorithm.
Design of the 3-Dimensional Real Time Disparity Estimation using Stereo Camera
Hong, Dooil,Woo, Kwangjae,Kim, Juhyun,Kang, Bongsoon 동아대학교 정보기술연구소 2003 情報技術硏究所論文誌 Vol.10 No.2
본 논문은 스테레오 카메라에서 얻은 2개의 흑백 영상을 이용, disparity algorithm을 바탕으로 영상에 나타난 물체의 깊이 정보를 영상의 밝고 어두운 정도로 나타낼 수 있는 방법을 제안한다. 이미지는 64-level의 밝기를 가지며 제안된 방법을 이용, 실시간 동작이 가능한 하드웨어 설계 및 구현을 실현한다. 실시간 동작을 위해 본 논문에서는 window matching방법대신 수직축 strip 구조를 이용하여 영상들의 유사 정도를 계산하였다. 물체의 거리 정보를 흑백 영상으로 변환하여 가까이 있는 물체는 밝게, 멀리 있는 물체는 어둡게 나타낼 수 있도록 하여 각종 영상장치에서 확인할 수 있도록 하였다. 본 논문에서 제안한 방법의 하드웨어는 15 frame/sec의 동작을 하도록 설계하였으며 VHDL로 설계하였고 Altera APEX20K1000EBC652-3의 device를 사용하여 검증하였으며, Hynix 0.35um CB35 ASIX library와 256PQFP package를 이용하여 IC로 제작하였다.
위상 교정 디지털 필터를 이용한 최적화된 수평축 영상 축소기의 하드웨어 설계 및 구현
홍두일,이봉근,강봉순,홍창희 동아대학교 정보기술연구소 2002 情報技術硏究所論文誌 Vol.9 No.2
In this paper, we propose a hardware implementation of optimized image downscaler. This image downscaler uses phase correction digital filters for horizontal scalings. It improves scaling precisions and decreases the loss of data, compared with pixel drop. In order to achieve the optimized hardware, digital filters are implemented by the multiplexer -adder architecture instead of adder - multiplexer. This image downscaler is designed by using the Verilog-HDL and verified by Xilinx Virtex XCV 2000E-6BG560 FPGA and ITU-R BT.601.
창간 유사도를 이용한 실시간 Disparity Estimator의 설계
홍두일,강봉순,홍창희 동아대학교 정보기술연구소 2002 情報技術硏究所論文誌 Vol.10 No.1
In this paper, we propose the disparity estimator that analyze depth data of stereo image using a disparity algorithm. Conventional method uses matching windows inside images and moves to windows from left to right based on searching steps. In this method, hardware requires huge buffers for real time processing. This paper adopts a vertical strip structure. In the proposal method, we can be possible a real time processing in optimized hardware. This disparity estimator is designed by using the VHDL and synthesized into gate by using the Samsung 0.65um KG75 library.
변형수,홍두일,강봉순 동아대학교 정보기술연구소 2002 情報技術硏究所論文誌 Vol.10 No.1
The color temperature model is based on the relationship between the temperature of a theoretical standardized material, called a black body radiator, and the energy distribution of its emitted light as the radiator is brought to increasingly higher temperatures, measured in Kelvin(K). The color-temperature conversion system is equipment that was converted the color-temperature of input image into user-wanted color-temperature in multimedia display equipment. This system was mentioned in reference^(1-4). This system operates using the relations between chromaticity coordinators of input image and user-wanted color temperature. In this paper, when users determine mapping of color-temperature that they want, the problem that the unnatural image occurred is modified, and the new color-temperature mapping method of the direction that users prefer is added. The proposed method is verified by fLCD-TV system using Xilinx Virtex FPGA XCV2000E-6BG560 that has 1344*806 resolution and requires a high-speed 65MHz operation.
Design and Implementation of the Real Time Disparity Estimation
Woo, Kwangjae,Hong, Dooil,Kwak, SungMin,Kim, Juhyun,Kang, Bongsoon 동아대학교 정보기술연구소 2003 情報技術硏究所論文誌 Vol.10 No.2
본 논문은 disparity 알고리듬에서 두개의 영상을 이용하여 문체의 깊이 정보를 분석하는 disparity decision system을 제안한다. 제안된 system은 실시간 처리를 위하여 유사한 pixel의 계산에 vertical strip 구조를 사용한다. 본 논문에서 제안한 방법의 system은 15 frame/sec의 동작을 하도록 설계하였으며 영상의 깊이 정보는 display 장치들을 사용하여 확인할 수 있다. 본 논문에서 제안한 하드웨어는 VHDL로 설계되었으며 Altera APEX20K1000EBC652-3의 device를 사용하여 검증하였다.
우광제,홍두일,강봉순 동아대학교 정보기술연구소 2002 情報技術硏究所論文誌 Vol.10 No.1
This paper is about square root system using gepyung's method. Designed square system is compared with the existing method that piecewise linear methods, Newton-Raphson algorithm, for example. The proposed algorithm have a strong point, hardware complexity and no error rate compared with the existing algorithm. This system is designed with VHDL and performed circuit synthesis using Samsung 0.35㎛ std90 library and Synopsys Design Analyzer.
Non-restoring Division 알고리즘을 이용한 실시간 나눗셈기의 하드웨어 최적화에 관한 연구
변형수,홍두일,이봉근,강봉순 동아대학교 정보기술연구소 2001 情報通信硏究所論文誌 Vol.9 No.1
This paper proposes the optimized hardware design of realtime divider using the non-restoring division algorithm. We also compare the non-restoring divison algorithm with the restoring division algorithm accroing to the pipeline stage. The proposed non-restoring divider reduced 25% in the hardware complexity, compared with the restoring algorithm. This propsoed divider is designed by using the VHDL and synthesized into gates by using the Synopsys synthesizer with the Samsung 0.35um STD90 library.
오차를 최소화한 Video Encoder를 위한 Chrominance Filter의 설계
김주현,홍두일,강봉순 동아대학교 정보기술연구소 2003 情報技術硏究所論文誌 Vol.10 No.2
In this paper, we propose hardware structure of chrominance filter for the video encoder which is operated in 27 MHz and satisfied with ITU-R BT.470, the standard of the conventional television system. The structure of the filter is cascade form and are focus on minimizing error for the filter by ±l LSB. The filter coefficients consist of n-th power of 2, and the size of hardware can be reduced by using shifter and adder without multiplier. The proposed chrominance filter is designed by using MATLAB and hardware description language VHDL. Synopsys Design Analyzer and Samsung STD90(0.35㎛, 3.3V) cell library are used for synthesis.