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직접전력변환 방식을 이용한 전압 sag/swell 보상기의 구현
차한주(Han-ju Cha),이대동(Dae-dong Lee) 대한전기학회 2006 대한전기학회 학술대회 논문집 Vol.2006 No.7
In this paper, a new single phase voltage sag/swell compensator using direct power conversion is introduced. A new compensator consists of input/output filter, series transformer and direct ac-ac converter, which is a single-phase back-to-back PWM converter without de-link capacitors. Advantages of the proposed compensator include: simple power circuit by eliminating de-link electrolytic capacitors and thereby, improved reliability and increased life time of the entire compensator; simple PWM strategy to compensate voltage sag/swell at the same time and reduced switching losses in the ac-ac converter. Further, the proposed scheme is able to adopt simple switch commutation method without requiring complex four-step commutation method commonly required in the direct power conversion. Simulation results are shown to demonstrate the advantages of the new compensator and PWM strategy.
직접전력변환 방식을 이용한 새로운 전압 sag/swell 보상기
차한주(Han-ju Cha),이대동(Dae-dong Lee) 대한전기학회 2006 대한전기학회 학술대회 논문집 Vol.2006 No.4
In this paper, a new single phase voltage sag/swell compensator using direct power conversion is introduced. A new compensator consists of input/output filter, series transformer and direct ac-ac converter, which is a single-phase back-to-back PWM converter without dc-link capacitors. Advantages of the proposed compensator include: simple power circuit by eliminating de-link electrolytic capacitors and thereby, improved reliability and increased life time of the entire compensator; simple PWM strategy to compensate voltage sag/swell at the same time and reduced switching losses in the ac-ac converter. Further, the proposed scheme is able to adopt simple switch commutation method without requiring complex four-step commutation method commonly required in the direct power conversion. Simulation results are shown to demonstrate the advantages of the new compensator and PWM strategy.
디지털제어 DC-DC컨버터로 구성된 계통연계 연료전지발전 시뮬레이션모델 개발
주영아(Young-Ah Ju),차민영(Min-Young Cha),한병문(Byung-Moon Han),강태섭(Tae-Sub Kang),차한주(Han-Ju Cha) 대한전기학회 2009 전기학회논문지 Vol.58 No.9
This paper proposes a new power conditioning system for the fuel cell power generation, which consists of a ZVS DC-DC converter and 3-phase inverter. The ZVS DC-DC converter with a digital controller boosts the fuel cell voltage of 26-50V up to 400V, and the grid-tie inverter controls the active power delivered to the grid. The operation of proposed power conditioning system was verified through simulations with PSCAD/EMTDC software. The feasibility of hardware implementation was verified through experimental works with a laboratory prototype, which was built with 1.2㎾ PEM fuel-cell stack, 1㎾ DC-DC converter, and 3㎾ PWM inverter. The proposed system can be utilized to commercialize an interconnection system for the fuel-cell power generation.
3상 정류기부하에 대한 수동 고조파필터의 해석 및 설계
조영식(Young-Sik Cho),차한주(Han-Ju Cha) 대한전기학회 2009 전기학회논문지 P Vol.58 No.3
This paper presents an analytical design method of a passive harmonic filter for a three-phase diode rectifier and uses a new transfer function approach in the analysis and design. The transfer function approach derives an analytical formulation of an utility system including passive filters with a basis of Laplace transform and provides a graphical formulation so that a visualized insight into an interaction between individual filter and system response can be attainted. Harmonic impedance, voltage division and current division transfer function are used as a design tool, which makes a calculated filter parameters to satisfy IEEE-519 distortion limits. A simple five-step design procedure is introduced in the filter design, which consists of system analysis, selection of PCC(Point of Common Coupling), filter specification calculation, appropriate filter design for system and filter implementation. Philosophy governing the design procedure is based on a numerical/graphical iterative solution, trial and error with visualization feed-back based on "algebra on the graph". Finally, performance of the designed passive harmonic filter is verified by experiment and shows that 5th, 7th, 9th, 11th and 13th harmonics are decreased within IEEE-519 distortion limits, respectively.
지/단락실증시험에서 MW급 계통연계형 ESS 절연/보호시스템 성능 분석에 관한 연구
김진태,이승용,박상진,차한주,김수열,Kim, Jin-Tae,Lee, Seung-Yong,Park, Sang-Jin,Cha, Han-Ju,Kim, Soo-Yeol 한국전력공사 2020 KEPCO Journal on electric power and energy Vol.6 No.2
With recent ESS (Energy Storage System) fire accident, the fault protection performance is becoming more important. However, there has never been any experiments with the protection performance on the faults in the ESS system level. In this study, the effect of AC ground fault and IGBT (Insulated Gate Bipolar mode Transistor) short-circuit failure on MW class ESS was performed experimentally for the first time in the world. First of all, the effect of the AC single line ground fault on battery was analyzed. Moreover, the transient voltage was investigated as a function of the battery capacity and the power level. Finally, the breaking capability and insulation performance of ESS were examined under PCS short-circuit fault condition. Through the tests, it was found that ESS protection system safely blocked the faulty current regardless of the faults, whereas the electronic parts such as IGBT and MC (Magnetic Contactor) were broken by the fault current. Also, the electrical breakdown in ESS resulted from the transient voltage during the protection process.
주파수 변동시 불평형 전압에 강인한 DSC-PLL 설계 연구
이재도(Jae Do Lee),차한주(Han Ju Cha) 대한전기학회 2018 전기학회논문지 Vol.67 No.11
In this paper, the design of robust DSC-PLL(Delayed Signal Cancellation Phase Locked Loop) is proposed for coping with frequency variation. This method shows significant performance for detection of fundamental positive sequence component voltage when the grid voltage is polluted by grid unbalance and frequency variation. The feedback frequency estimation of DSC-PLL is tracking the drift in the phase by unbalance and frequency variation. The robust DSC PLL is to present the analysis on method and performance under frequency variations. These compensation algorithms can correct for discrepancies of changing the frequency within maximum 193[ms] and improve traditional DSC-PLL. Linear interpolation method is adopted to reduce the discretized errors in the digital implementation of the PLL. For verification of robust characteristic, PLL methods are implemented on FPGA with a discrete fixed point based. The proposed method is validated by both Matlab/Simulink and experimental results based on FPGA(XC7Z030).