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Planar MOSFET에서 측정을 통한 기생 커패시턴스 추출 방법
전상빈(Sangbin Jeon),유성원(Sungwon Yoo),고형우(Hyoungwoo Ko),고결(Kyul Ko),신형철(Hyungcheol Shin) 대한전자공학회 2015 대한전자공학회 학술대회 Vol.2015 No.11
In this study, we suggested a method for extracting parasitic capacitance at planar MOSFET. Under different gate voltage, capacitance of MOSFET changes. Thus measurement of capacitance of gate to drain region at varying gate voltage, allowed to extract parasitic capacitance.
정확환 Field Enhancement Factor를 고려하여 트랩 종류에 따른 트랩사이 거리 추출
전현옥(Hyunok Jeon),유성원(Sung-Won Yoo),이현슬(Hyunseul Lee),서영수(Youngsoo Seo),전상빈(Sangbin Jeon),고형우(Hyungwoo Ko),고결(Kyul Ko),신형철(Hyungcheol Shin) 대한전자공학회 2015 대한전자공학회 학술대회 Vol.2015 No.6
The characteristics of oxide slow trap was extracted from gate-induced drain leakage (GIDL) random telegraph noise (RTN) measurement. The ratio of trap-assisted tunneling (TAT) GIDL current before and after carrier capture into the slow trap was derived with consideration to the type of slow trap. And, the distance between fast and slow trap was extracted and compared in case of acceptor-like and donor-like trap based on the measurement and equations derived from the accurate field enhancement factor. Finally, the relative positions of the two trap can be determined at the gate-to-drain overlap region with consideration to the type of slow trap.
실리콘 내부에 있는 slow trap에 의한 TAT 전류 변화 분석
고결(Kyul Ko),유성원(Sung-Won Yoo),이현슬(Hyunseul Lee),서영수(Youngsoo Seo),전상빈(Sangbin Jeon),고형우(Hyungwoo Ko),전현옥(Jeon-Hyun Ok),신형철(Hyungcheol Shin) 대한전자공학회 2015 대한전자공학회 학술대회 Vol.2015 No.6
In this paper, we present an analysis of the trap-assisted tunneling (TAT) area on gate-induced drain leakage (GIDL) current variation by the slow trap in silicon using an analytical equations. And, TAT current variation is compared with the type of charge carrier. Finally, we compared TAT GIDL current variation by slow trap in oxide with silicon region depending on the perpendicular distance of the slow trap from the interface and temperature.