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트리구조망에서 시분할 CDMA 기반 매체접속제어 프로토콜
임교묵(Kyomuk Lim),민승화(Seung-hwa Min),조호신(Ho-shin Cho),손권(Kweon Son),이상국(Sang-Kug Lee),장윤선(Youn-seon Jang) 대한전자공학회 2011 대한전자공학회 학술대회 Vol.2011 No.12
본 논문에서는, Tree구조의 Time-Scheduled CDMA MAC 프로토콜을 제안하였다. 중앙집중형 네트워크에서 충돌을 피하기 위하여 각 레벨에서는 스케줄 된 time-slot을 할당하고, 같은 레벨의 node들 끼리는 CDMA 방식을 적용한다. 또한, sleep-mode를 통하여 에너지 절약을 기대할 수 있다. 제안하는 프로토콜을 평가한 결과 하나의 node에 단일 code를 할당하는 single-code방식이 여러 개의 code를 할당하는 multi-code방식 보다 성능이 우수하다는 것과 기존의 경쟁기반 프로토콜인 slotted FAMA 방식과 비교하여 매우 뛰어난 성능을 나타내는 것을 알 수 있었다.
서진덕,임교묵,이상민,안재현,홍석준,유형중,정석원,박선길,조동일,고형호 대한전자공학회 2013 Journal of semiconductor technology and science Vol.13 No.1
We describe a neural stimulator front-endwith arbitrary stimulation waveform generator andadaptive supply regulator (ASR) for visual prosthesis. Each pixel circuit generates arbitrary currentwaveform with 5 bit programmable amplitude. TheASR provides the internal supply voltage regulated tothe minimum required voltage for stimulation. Theprototype is implemented in 0.35 μm CMOS with HVoption and occupies 2.94 mm2 including I/Os.
A 16-channel Neural Stimulator IC with DAC Sharing Scheme for Artificial Retinal Prostheses
석창호,김현호,임승현,송하룡,임교묵,구용숙,구교인,조동일,고형호 대한전자공학회 2014 Journal of semiconductor technology and science Vol.14 No.5
The neural stimulators have been employed to the visual prostheses system based on the functional electrical stimulation (FES). Due to the size limitation of the implantable device, the smaller area of the unit current driver pixel is highly desired for higher resolution current stimulation system. This paper presents a 16-channel compact current-mode neural stimulator IC with digital to analog converter (DAC) sharing scheme for artificial retinal prostheses. The individual pixel circuits in the stimulator IC share a single 6 bit DAC using the sample-and-hold scheme. The DAC sharing scheme enables the simultaneous stimulation on multiple active pixels with a single DAC while maintaining small size and low power. The layout size of the stimulator circuit with the DAC sharing scheme is reduced to be 51.98 %, compared to the conventional scheme. The stimulator IC is designed using standard 0.18 μm 1P6M process. The chip size except the I/O cells is 437 μm 501 μm.
서진덕 ( Jin Deok Seo ),임교묵 ( Kyo Muk Lim ),고형호 ( Hyoung Ho Ko ) 한국센서학회 2012 센서학회지 Vol.21 No.3
This paper presents frequency response compensation technique, and a self-oscillation circuit for capacitive microresonator with the compensation technique using programmable capacitor array, to compensate for the frequency response distorted by parasitic capacitances, and to obtain stable oscillation condition. The parasitic capacitances between the actuation input port and capacitive output port distort the frequency response of the microresonator. The distorted non-ideal frequency response can be compensated using two programmable capacitor arrays, which are connected between anti-phased actuation input port and capacitive output port. The simulation model includes the whole microresonator system, which consists of mechanical structure, transimpedance amplifier with automatic gain control, actuation driver and compensation circuit. The compensation operation and oscillation output of the system is verified with the simulation results.