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이용회(Lee Yong Hui),이재영(Yi Jae Young),이천희(Yi Cheon Hee) 한국정보과학회 2000 한국정보과학회 학술발표논문집 Vol.27 No.2Ⅰ
We are studied on the performance optimized synthesis and mapping of design on to one or more FPGA device. our multi-phased approach optimized the key parameters that affect performance by adequately modeling the impact on wire length, routability, and performance during technology mapping to produce designs that have high performance and high routability potential.