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Noise Interpolation of MOSFET in Moderate Inversion and Its Verification in Low Noise Amplifier
송익현(Ickhyun Song),구민석(Min Suk Koo),정학철(Hakchul Jung),이상훈(Sanghoon Lee),Shen Yehao,전희석(Hee Sauk Jhon),신형철(Hyungcheol Shin) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
MOSFET noise in moderate inversion region is interpolated using two noise models in the regions of subthreshold and strong inversion. With these channel noise value, a CMOS low noise amplifier (LNA) operating in moderate inversion region is designed for verification and its noise characteristic is presented.
Low Cost CMOS LNA Design Using On-Chip Size Efficient Inductors
전희석(Hee-Sauk Jhon),송익현(Ickhyun Song),윤여남(Yeonam Yun),구민석(Minsuk Koo),정학철(Hakchul Jung),신형철(Hyungcheol Shin) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
This paper presents the implementation technique to reduce circuit area occupation in designing Low Noise Amplifier (LNA) using size efficient inductors. We applied vertical shunt symmetric and helical inductor to match the input and output in 2.4 ㎓ CMOS LNA to reduce the circuit area. In this paper, the case of conventional LNA using asymmetric inductor, and that of ones using vertical shunt symmetrical and helical inductor with a relatively higher number of turns have been compared in order to present a size efficient CMOS LNA design method while still retaining the circuit operation characteristics.
윤지원(Ji-Won Yoon),황선주(Sun-Joo Whang),송익현(Ickhyun Song) 대한전자공학회 2022 대한전자공학회 학술대회 Vol.2022 No.11
In this paper, we present a reconfigurable CMOS rectifier with a function of generating steady output in a relatively wide range of input power. The proposed rectifier consists of 3 CCDD (Cross-Coupled Differential Drive) stages for delivering output power and an auxiliary rectifier for operating logic. Therefore, this circuit has an advantage in that it operates the logic without using an external power source. In addition, the complexity of system configuration can be simplified since the rectifier generates a steady output without using an additional device.
이정민(Jeong-Min Lee),정진률(Jin-Ryul Jung),송익현(Ickhyun Song) 대한전자공학회 2022 대한전자공학회 학술대회 Vol.2022 No.11
In this paper, we introduce a LNA(Low Noise Amplifier) analog circuit optimization process using DDPG(Deep Deterministic Policy Gradient) reinforcement learning technique. Compared to the traditional human resource-based optimization process, machine learning method that we propose has considerably increased the final circuit performance.