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고속 동작 및 저전압 PLL을 위한 위상 주파수 검출기 설계
손위(Sun Wei),서해준(Hae-Jun Seo),김영운(Young-Woon Kim),황금주(Kum-Joo Hwang),조태원(Tae-Won Cho) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
This paper presents a new PFD circuit which is suitable for the high speed and low voltage PLL. The proposed PFD can operate at 2.2㎓ with a supply voltage of 1.5V and average power dissipation of 0.165㎽. Moreover, the PFD decreases the dead zone to 1㎰. The proposed PFD is designed in a standard CMOS 0.18㎛ technology and simulated by HSPICE.
손위(Sun Wei),김영운(Young-Woon Kim),김영복(Young-Bok Kim),서해준(Hae-Jun Seo),황금주(Kum-Joo Hwang),조태원(Tae-Won Cho) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
This paper presents a new simple charge-pump circuit, which is suitable for high speed PLL circuit and operates at a low supply voltage. The charge-pump operates at 800㎒ with a supply voltage of 1.5V. Moreover, the output voltage of the proposed charge-pump circuit has a stable voltage step. The charge-pump is designed in a standard CMOS 0.25㎛ technology and simulated by HSPICE.
김영운(Young-Woon Kim),손위(Wei Sun),서해준(Hae-Jun Seo),조태원(Tae-Won Cho) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.11
Full adders are important components in applications such as digital signal processors and microprocessors. Thus It is important to improve the power dissipation and operating speed for designing a full adder. We propose a high speed full adder with modified version of conventional ratioed logic and pass transistor logic. The proposed adder has the advantages over the conventional CMOS, TGA, 14T logic. The delay time is improved by 13% comparing to the average value and PDP(Power Delay Product) is improved by 9% comparing to the average value. The physical design has been evaluated using HSPICE.