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Redundant 2진 구조를 이용한 8 × 8-Bit 복소수 승산기의 설계
라승수,김정범 강원대학교 정보통신연구소 2003 정보통신논문지 Vol.7 No.-
A redundant binary (RB) architecture, which is optimized for the fast CMOS parallel multiplier, is proposed. This architecture enables one of to convert a pair of partial products in normal binary (NB) from to one RB number with no additional circuits. We improved the RB adder circuit so that it can make a fast addition of the RB partial products. We also simplified the converter that converts the final RB number into the corresponding NB number. The carry propagation path of the converter circuit is carried out with only a multiplexer. An 8×8-bit complex multiplier is designed with this architecture. It is fabricated by 0.6 um standard CMOS process with triple metal technology. The validity and effectiveness of the designed multiplier are verified through the MAX PLUS-Ⅱ and HSPICE simulation. The active area size is 1.55×1.45 mm2 and the number of transistors is 16,323. Under the condition of 3.3V supply voltage, the chip achieves 7.5 ns multiplication time.