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Guannan Wei,Yung C. Liang,Ganesh S. Samudra 전력전자학회 2011 ICPE(ISPE)논문집 Vol.2011 No.5
This paper presents a practical methodology for realistic simulation on reverse characteristics of Wide Bandgap (WBG) SiC/GaN p-n junctions. The adjustment on certain physic-based model parameters, such as the trap density and photo-generation for SiC junction, and impact ionization coefficients and critical field for GaN junction are described. The adjusted parameters were used in Synopsys Medici simulation to obtain a realistic p-n junction avalanche breakdown voltage. The simulation results were verified through benchmarking against independent data reported by others.
Realistic Simulations on Reverse Junction Characteristics of SiC and GaN Power Semiconductor Devices
Wei, Guannan,Liang, Yung C.,Samudra, Ganesh S. The Korean Institute of Power Electronics 2012 JOURNAL OF POWER ELECTRONICS Vol.12 No.1
This paper presents a practical methodology for realistic simulation on reverse characteristics of Wide Bandgap (WBG) SiC and GaN p-n junctions. The adjustment on certain physic-based model parameters, such as the trap density and photo-generation for SiC junction, and impact ionization coefficients and critical field for GaN junction are described. The adjusted parameters were used in Synopsys Medici simulation to obtain a realistic p-n junction avalanche breakdown voltage. The simulation results were verified through benchmarking against independent data reported by others.
Realistic Simulations on Reverse Junction Characteristics of SiC and GaN Power Semiconductor Devices
Guannan Wei,Yung C. Liang,Ganesh S. Samudra 전력전자학회 2012 JOURNAL OF POWER ELECTRONICS Vol.12 No.1
This paper presents a practical methodology for realistic simulation on reverse characteristics of Wide Bandgap (WBG) SiC and GaN p-n junctions. The adjustment on certain physic-based model parameters, such as the trap density and photo-generation for SiC junction, and impact ionization coefficients and critical field for GaN junction are described. The adjusted parameters were used in Synopsys Medici simulation to obtain a realistic p-n junction avalanche breakdown voltage. The simulation results were verified through benchmarking against independent data reported by others.
Miao Cui,Qinglei Bu,Yutao Cai,Ruize Sun,Wen Liu,Huiqing Wen,Sang Lam,Yung. C. Liang,Ivona Z. Mitrovic,Stephen Taylor,Paul R. Chalker,Cezhou Zhao 전력전자학회 2019 ICPE(ISPE)논문집 Vol.2019 No.5
This study proposed a 100 kHz, 5V/11V boost converter with an integrated gate driver for a power switching device using recessed E-mode MIS-HFETs. The integrated gate driver consisting of multi-stages DCFL (Direct-Coupled FET Logic) inverters and a buffer stage, has large input swing (up to 10 V) and wide noise margin with gate dielectric, which benefits applications requiring large gate swing without any additional drivers or level shifters. The impact of transistor size on rise times and fall times have been studied. Either buffer stage or larger width of DCFL inverter can reduce rise times from 2.4 μs to less than 0.5 μs at 100 kHz, so the output voltage of boost converter is increased by 10 % at a duty cycle of 0.7. However, large buffer width can result in high gate overshoot and oscillation, indicating careful design to balance switching speed and oscillation.