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Improvement of parallel processing performance by using two kinds of Huge Page
Takafumi Fukunaga,Toshinori Sueyoshi 제어로봇시스템학회 2008 제어로봇시스템학회 국제학술대회 논문집 Vol.2008 No.10
A main memory capacity in PC continues to increase because the memory requirements which applications need get bigger and bigger. It is easy to expand main memory. But TLB is very scarce as before. Under these circumstances, the uses of Huge Page reduce TLB misses by reducing the numbers of needed entries of TLB, consequently give applications which need large memories a good effect in regard to execution speed. But the uses of Huge Page cause large useless memory because operating system round up used memory to a multiple of Huge Page size. Then we propose a method which can use Huge Page while saving memories on IA-64. This proposed method allocates another smaller Huge Page which we added this time to a fragment in the back part of used memory. As a result of experimentation, proposed method show the same speed as the original system and good results in regard to memory requirements. This time we applied this proposed method to PC cluster as parallel processing programs need large memories generally and measured parallel processing performance.
Improvement of execution efficiency on a massively parallel SIMD accelerator
Mitsutaka Nakano,Masahiro Iida,Toshinori Sueyoshi 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
SIMD (Single Instruction/Multiple Data) type processors have the advantage of smaller area as compared with a general processor, DSP and many MIMD (Multiple Instruction/Multiple Data) type processors. On the other hand, the performance depends on the parallel degree of data in an application. MX Core which was developed by Renesas technology Corp., is a massively parallel SIMD type accelerator. We propose a method to improve execution efficiency of the MX Core in this paper. Our methodology includes optimization of calculation precision and change data transfer structure to MIMD type. As a result of evaluation, we improved parallel operation degree. The proposal structure reduced data transfer pro-cessings of IMDCT by 90%, and speed up processing time of IMDCT by 2.65 times compared with traditional implementation of the MX Core.
Generalized Isomorphism between Synchronous Circuits and State Machines
Shunji Nishimura,Motoki Amagasaki,Toshinori Sueyoshi 대한전자공학회 2015 ITC-CSCC :International Technical Conference on Ci Vol.2015 No.6
This paper proposes a new model which describes a circuit and its behavior by adopting a category theory. In this model, we define a new class of synchronous elements “comprehensive latches”, and show that for any such comprehensive latch synchronous circuit, there is a state machine that behaves similarly to the circuit. That kind of isomorphism is well-known only for D-FlipFlop synchronous circuit, and our isomorphism is its generalization since comprehensive latches include D-FlipFlops. The key idea of our isomorphism is that a state machine is synchronized by a natural transformation (categorical term) in an analogous way of that circuit is synchronized by a synchronous element. D-Latches are also elements of our comprehensive latches, and thus, for a given D-Latch synchronous circuit, the isomorphism provides a state machine correspond to the circuit.