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A Novel Selective Etching Technique for Chip-scale Metal MEMS Integration
Lee, Hocheol,Bifano, Tomas G. 한밭대학교 생산기반기술연구소 2004 생산기반기술연구소 논문집 Vol.5 No.1
Metal-based micro mirror array needs a flat CMOS electronic circuit with mirror-like surface topography. Therefore, chemical mechanical polishing can be applied to remove a couple of micrometer size of bumps of foundry chip. To overcome the tendency for tilt error in the CMOS chip planarization, the approach is to sputter a thick layer of silicon nitride at low temperature and to surround the CMOS chip with dummy silicon pieces to define a polishing plane. Therefore, the bumps height of 1.8㎛ is removed by the planarization. Measurement using white light interferometer shows the root mean square error of the chip flatness less than 100nm including tilt, curvature term. After planarization, to build interconnections between MEMS structures and CMOS electronics, 44㎛ via holes are anisotropically etched using metal mask with Lift-off and Reactive ion Etching Process. Subsequent metal deposition using lift-off process will form both electrode and electrical connections to CMOS electronics. Due to the small size of the CMOS chip, the surface tension causes strong edge beads, which make several challenging patterning technique. The process details about minimizing edge-beads, and finding optimum recipe for no residual pattern arc studied.