http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
Floorplanning with Multi-Phase Clock assignment based on Force Directed Method
Tetsutarou Hara,Katsumi Harashima 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
Module placement is an important phase for VLSI layout design. Conventional methods for packing problem minimize area and wire-length mainly. Additionally we assign automatically Multi-Phase Clocks each circuit modules to increase processing speed. An effective clock assignment for Multi-Phase Clock VLSI is made by evaluating signal flows. This paper proposes a block packing method using Force Directed Model(FDM) with Hierarchical Clustering(HC). The method assembles modules having strong connection on a cluster. By assigning different clock to each module in a cluster, processing speed of every cluster becomes faster.
Efficient Floorplanning by O-Tree with Genetic Algorithm
Tetsutarou Hara,Katsumi Harashima 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
Module placement is an important phase for VLSI layout design. However, huge time is necessary to obtain the optimal layout. This paper proposes a block packing method using O-Tree with Genetic Algorithm. O-Tree can transform a code into a placement in linear time to the number of modules. Moreover, Genetic Algorithm is effective for searching a good layout because it can search two or more layouts concurrently. In experiment, we have confirmed to obtain nearly optimal packing results efficiently.