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The Design of the Clock Recovery Using SRTS Technique for ATM-UNI System
Tenqchen,Shing,Lin,Sun Ting,ChEng,Yiuhchi,Hwang,Gwo Haw 대한전자공학회 1997 ICVC : International Conference on VLSI and CAD Vol.5 No.1
The Synchronous Residual Time Stamp (SRTS) technique has become the ITU-T standard of the AAL type 1 clock recovery. In this paper, the implementation of SRTS for clock recovery is proposed for the verification of this new technology. To reduce the area and cost of the whole system, the all digital PLL (ADPLL) circuit is implemented together with the transmitter and receiver side. The SRTS incorporated the advantages of both Synchronous Frequency Encoding Technique (SFET) and Time Stamp (TS) is presented. The method to measure the frequency difference is similar to that of TS; however, it keeps the efficiency of SFET. The application of this circuit developed for the ATM UNI (user network interface) system is especially for the single chip of cell assembler and cell disassembler shown in this paper.
Hwang,Gwo Haur,Shen,Wen Zen,Tenqchen,Shing 대한전자공학회 1995 ICVC : International Conference on VLSI and CAD Vol.4 No.1
In this paper, a complete PLA break fault ATPG system, PLABEK, is proposed. PLABEK contains four main parts : 1) break fault collapsing; 2) pruning algorithm based test pair generation; 3) serial fault-injection parallel-bit-operation event-driven break fault simulation; and 4) testability-measure-based fault ordering. Experimental results show that PLABEK can generate complete compact test sequences for PLA's break faults very fast.