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A Symmetrical Floating Impedance Scaling Circuit with Improved Low-frequency Characteristics
Fujihiko MATSUMOTO,Syuzo NISHIOKA,Shota MATSUO,Takeshi OHBUCHI 대한전자공학회 2017 IEIE Transactions on Smart Processing & Computing Vol.6 No.6
Impedance scaling techniques are known as methods to realize large capacitance with a small capacitor. Recently, a symmetrical floating impedance scaling (SFIS) circuit was proposed. However, the circuit has restrictions on operations at a lower frequency. In this paper, improvement techniques for low-frequency characteristics of the SFIS circuit are proposed. In order to enhance the terminal resistance, a negative impedance converter (NIC) block is employed in the SFIS circuit. In addition, cascode transistors are introduced to enhance the internal resistance associated with a capacitor in the SFIS circuit. The proposed techniques make the pole frequency lower. The proposed SFIS circuit is applied to a third-order Chebyshev filter via simulation. Cutoff frequency fc of the filter is set to 100 Hz, and the passband ripple of the filter is set to 0.5 dB. Simulation results show that the filter employing the proposed SFIS circuit is superior to a conventional one.