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Series resistance in different operation regime of junctionless transistors
Jeon, Dae-Young,Park, So Jeong,Mouis, Mireille,Barraud, Sylvain,Kim, Gyu-Tae,Ghibaudo, Gé,rard Elsevier 2018 Solid-state electronics Vol.141 No.-
<P><B>Abstract</B></P> <P>Operation mode dependent series resistance (R<SUB>sd</SUB>) behavior of junctionless transistors (JLTs) has been discussed in detail. R<SUB>sd</SUB> was increased for decreasing gate bias in bulk conduction regime, while a constant value of R<SUB>sd</SUB> was found in accumulation operation mode. Those results were compared to conventional inversion-mode (IM) transistors, verified by 2D numerical simulation and temperature dependence of extracted R<SUB>sd</SUB>. This work provides key information for a better understanding of JLT operation affected by R<SUB>sd</SUB> effects with different state of conduction channel.</P> <P><B>Highlights</B></P> <P> <UL> <LI> Series resistance (R<SUB>sd</SUB>) on different operation regimes of junctionless transistors (JLTs) was discussed. </LI> <LI> A constant R<SUB>sd</SUB> was extracted in near flat-band or accumulation operation regime. </LI> <LI> However, R<SUB>sd</SUB> was increased significantly in partially depleted mode operation. </LI> <LI> Unique operation principle with bulk neutral conduction in JLTs makes the results. </LI> <LI> Those results were verified by 2D numerical simulation and temperature dependence of R<SUB>sd</SUB>. </LI> </UL> </P>
Flat-band voltage and low-field mobility analysis of junctionless transistors under low-temperature
Joo, Min-Kyu,Mouis, Mireille,Jeon, Dae-Young,Barraud, Sylvain,Park, So Jeong,Kim, Gyu-Tae,Ghibaudo, Gé,rard Institute of Physics 2014 Semiconductor science and technology Vol.29 No.4
<P>This paper presents the low-temperature characteristics of flat-band (<I>V</I><SUB>FB</SUB>) and low-field mobility in accumulation regime (µ<SUB>0_acc</SUB>) of n-type junctionless transistors (JLTs). To this end, split capacitance-to-voltage (<I>C–V</I>), dual gate coupling and low-temperature measurements were carried out to systematically investigate <I>V</I><SUB>FB</SUB>. Additionally, the gate oxide capacitance per unit area <I>C</I><SUB>ox</SUB> and the doping concentration <I>N</I><SUB>D</SUB> were evaluated as well. Accounting for the position of <I>V</I><SUB>FB</SUB> and the charge based analytical model of JLTs, bulk mobility (µ<SUB>B</SUB>) and µ<SUB>0_acc</SUB> were separately extracted in volume and surface conduction regime, respectively. Finally, the role of neutral scattering defects was found the most limiting factor concerning the degradation of µ<SUB>B</SUB> and µ<SUB>0_acc</SUB> with gate length in planar and tri-gate nanowire JLTs.</P>