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Jin-Woo Han,Seong-Wan Ryu,Chung-Jin Kim,Sung-Jin Choi,Sungho Kim,Jae-Hyuk Ahn,Dong-Hyun Kim,Kyu Jin Choi,Byung Jin Cho,Jin-Soo Kim,Kwang Hee Kim,Gi-Sung Lee,Jae-Sub Oh,Myeong-Ho Song,Yun Chang Park,Je IEEE 2009 IEEE transactions on electron devices Vol.56 No.4
<P>A band-offset-based unified-RAM (URAM) cell fabricated on a Si/Si<SUB>1-y</SUB>C<SUB>y</SUB> substrate is presented for the fusion of a nonvolatile memory (NVM) and a capacitorless 1T-DRAM. An oxide/nitride/oxide (O/N/O) gate dielectric and a floating-body are combined in a FinFET structure to perform URAM operation in a single transistor. The O/N/O layer is utilized as a charge trap layer for NVM, and the floating-body is used as an excess hole storage node for capacitorless 1T-DRAM. The introduction of a pseudomorphic SiC-based heteroepitaxial layer into the Si substrate provides band offset in a valence band. The FinFET fabricated on the energy-band-engineered Si<SUB>1-y</SUB>C<SUB>y</SUB> substrate allows hole accumulation in the channel for 1T-DRAM. The band-engineered URAM yields a cost-effective process that is compatible with a conventional body-tied FinFET SONOS. The fabricated URAM shows highly reliable NVM and high-speed 1T-DRAM operations in a single memory cell.</P>
Han, Jin-Woo,Ryu, Seong-Wan,Kim, Chung-Jin,Kim, Sungho,Im, Maesoon,Choi, Sung Jin,Kim, Jin Soo,Kim, Kwang Hee,Lee, Gi Sung,Oh, Jae Sub,Song, Myeong Ho,Park, Yun Chang,Kim, Jeoung Woo,Choi, Yang-Kyu IEEE 2008 IEEE electron device letters Vol.29 No.7
<P> Unified random access memory (URAM) is demonstrated for the first time. The novel partially depleted (PD) SONOS FinFET provides unified function of a high-speed capacitorless 1T DRAM and a nonvolatile memory (NVM). The combination of an oxide/nitride/oxide (O/N/O) layer and a floating-body facilitates URAM operation in PD SONOS FinFETs. An NVM function is achieved by FN tunneling into the O/N/O stack and, a 1T-DRAM function is achieved by excessive-hole accumulation in the PD body. The fabricated PD SONOS FinFET shows retention time exceeding 10 years for NVM operation and program/erase time below 6 ns for 1T-DRAM in a single-cell transistor. These two memory functions are guaranteed without disturbance between them. </P>
Fully Depleted Polysilicon TFTs for Capacitorless 1T-DRAM
Jin-Woo Han,Seong-Wan Ryu,Dong-Hyun Kim,Chung-Jin Kim,Sungho Kim,Dong-Il Moon,Sung-Jin Choi,Yang-Kyu Choi IEEE 2009 IEEE electron device letters Vol.30 No.7
<P>A capacitorless 1T-DRAM is fabricated on a fully depleted poly-Si thin-film transistor (TFT) template. A heavily doped back gate with a thin back-gate dielectric is employed to facilitate the formation of a deep potential well that retains excess holes. An asymmetric double gate (n<SUP>+</SUP> front gate and p<SUP>+</SUP> back gate) shows a wider sensing current window than a symmetric double gate (n<SUP>+</SUP> front gate and n<SUP>+</SUP> back gate). This is attributed to the inherent flatband voltage between the p<SUP>+</SUP> back gate and the channel inducing a deeper potential well, which allows capacitorless 1T-DRAM operation at a low back-gate voltage. The TFT capacitorless 1T-DRAM can be applied for future stackable memory for the ultrahigh density era.</P>
JIN-YEOL KIM,,KUNBAE NOH,CHULMIN CHOI,KARLA S. BRAMMER,MARIANA LOYA,LI-HAN CHEN,SUNGHO JIN,BRAMMER 성균관대학교(자연과학캠퍼스) 성균나노과학기술원 2010 NANO Vol.5 No.2
We have shown in this paper that the self-ordered pore structure of anodic aluminum oxide (AAO) can be utilized as a basis to conveniently form large-area Al2O3 nanowire arrays on a glass surface. An aluminum oxide nanowire array has been produced by aluminum film deposition on glass followed by anodization, then simple chemical etching. The glass surface as prepared is highly superhydrophobic, with a contact angle as high as 169°. The thinness (~ 340 nm) and vertical alignment of the aluminum oxide nanowires with empty spaces in-between essentially contribute to maintaining the optical transparency of the glass substrate. Interestingly, substantially suppressed UV transmission in the ~ 300–400 nm spectrum region was observed with the presence of the Al2O3 nanowires on the glass substrate. Such a durable surface ceramic nanowire structure can be useful for producing superhydrophobic, self-cleaning glasses with a variety of potential applications such as UV protecting glass windows for high rise buildings with reduced consumption of water and cleaning chemicals for positive environmental effects.
Colossal Magnetoresistance in La-Ca-Mn-O
Sungho Jin 한국자기학회 1997 Journal of Magnetics Vol.2 No.1
Very large change in electrical resistivity by several orders of magnitude is obtained when an external magnetic field is applied to the colossal magnetoresistance (CMR) materials such as La-Ca-Mn-O. The magnetoresistance is strongly temperature-dependent, and exhibits a sharp peak below room temperature, which can be shifted by adjusting the composition or processing parameters. The control of lattice geometry or strain, e.g., by chemical substitution, epitaxial growth or post-deposition anneal of thin films appears to be crucial in obtaining the CMR properties. The orders of magnitude change in electrical resistivity could be useful for various magnetic and electric device applications.
Jin, Ho,Nam, Jutaek,Park, Joonhyuck,Jung, Sungho,Im, Kyuhyun,Hur, Jaehyun,Park, Jong-Jin,Kim, Jong-Min,Kim, Sungjee Royal Society of Chemistry 2011 Chemical communications Vol.47 No.6
<P>A series of quantum dot (QD) ligands are reported that can make strong polyelectrolyte QD surfaces with sulfonates or quaternary ammoniums, which can endow QDs with excellent colloidal stability independent of the pH and ionic strength, minimal hydrodynamic size, and can be exploited to achieve stable and flexible bioconjugations and layer-by-layer assembly.</P> <P>Graphic Abstract</P><P>Strong polyelectrolyte quantum dot surface ligands with sulfonates or quaternary ammoniums are reported that can provide excellent colloidal stability, minimal hydrodynamic size, and applicability to stable and flexible bioconjugations and layer-by-layer assembly. <IMG SRC='http://pubs.rsc.org/services/images/RSCpubs.ePlatform.Service.FreeContent.ImageService.svc/ImageService/image/GA?id=c0cc04524a'> </P>
( Jin Kyung Park ),( Sungho Kim ),( Hee Jin Kim ),( Duk Hyun Lee ) 대한내과학회 2014 대한내과학회 추계학술대회 Vol.2014 No.1
Spontaneous rupture and bleeding of the kidney is a rare event and caused mostly by renal cell carcinoma, angiomyolipoma, vascular diseases or acquired cystic renal disease. We report a case of spontaneous renal rupture which occurred in 50-year-old woman with end-stage renal disease. Case: A 50-year-old woman with end-stage renal disease caused by chronic glomerulonephritis visited emergency room with severe left fi ank pain. She was on hemodialysis for 13 years and had no history of trauma. Computed tomography showed considerable hematoma on left pararenal area, atrophy of both kidneys and multiple small renal cysts. Emergent selective renal angiogram was performed and contrast leakage was seen at the upper pole of left kidney. Immediate left renal artery embolization was performed without any complication. The occurrence of acquired cysts in kidneys with primary chronic kidney disease is found in 10-95% of patients, depending on age (more frequent in the elderly), renal function (more frequent in advanced renal failure), and duration of renal failure/dialysis therapy. Clinical complications such as pain, hemorrhage, infection, malignancy, and nephrolithiasis can occur in acquired cystic renal disease. Some studies report that anticoagulant therapy or using heparin during hemodialysis is associated with the risk of cystic rupture and bleeding. The occurrence of spontaneous renal rupture should always be considered on regular hemodialysis patients when unexplained distress or fall of hemoglobin suddenly takes place.
Cho, Jin Woo,Ismail, Agus,Park, Se Jin,Kim, Woong,Yoon, Sungho,Min, Byoung Koun American Chemical Society 2013 ACS APPLIED MATERIALS & INTERFACES Vol.5 No.10
<P>Cu<SUB>2</SUB>ZnSnS<SUB>4</SUB> (CZTS) is a very promising semiconductor material when used for the absorber layer of thin film solar cells because it consists of only abundant and inexpensive elements. In addition, a low-cost solution process is applicable to the preparation of CZTS absorber films, which reduces the cost when this film is used for the production of thin film solar cells. To fabricate solution-processed CZTS thin film using an easily scalable and relatively safe method, we suggest a precursor solution paste coating method with a two-step heating process (oxidation and sulfurization). The synthesized CZTS film was observed to be composed of grains of a size of ∼300 nm, showing an overall densely packed morphology with some pores and voids. A solar cell device with this film as an absorber layer showed the highest efficiency of 3.02% with an open circuit voltage of 556 mV, a short current density of 13.5 mA/cm<SUP>2</SUP>, and a fill factor of 40.3%. We also noted the existence of Cd moieties and an inhomogeneous Zn distribution in the CZTS film, which may have been triggered by the presence of pores and voids in the CZTS film.</P><P><B>Graphic Abstract</B> <IMG SRC='http://pubs.acs.org/appl/literatum/publisher/achs/journals/content/aamick/2013/aamick.2013.5.issue-10/am401210w/production/images/medium/am-2013-01210w_0007.gif'></P><P><A href='http://pubs.acs.org/doi/suppl/10.1021/am401210w'>ACS Electronic Supporting Info</A></P>
Improvement of the Sensing Window on a Capacitorless 1T-DRAM of a FinFET-Based Unified RAM
Sung-Jin Choi,Jin-Woo Han,Chung-Jin Kim,Sungho Kim,Yang-Kyu Choi IEEE 2009 IEEE transactions on electron devices Vol.56 No.12
<P>A novel initialization concept is demonstrated to improve the program efficiency of the 1T-DRAM mode of unified random access memory (URAM). The proposed method involves boosting the gate-induced drain leakage current for the generation of excess holes by pretrapping electrons to the nitride layer prior to the activation of 1T-DRAM mode. The proposed initialization concept doubles the current sensing window in 1T-DRAM operation. Due to the potential for soft erasing caused by hot-hole injections into electrons that are trapped in the nitride during the P/E cycling of 1T-DRAM, immunity against soft erasing is confirmed through a dc stress measurement as well.</P>
Dopant-Segregated Schottky Source/Drain FinFET With a NiSi FUSI Gate and Reduced Leakage Current
Sung-Jin Choi,Jin-Woo Han,Sungho Kim,Dong-Il Moon,Moongyu Jang,Yang-Kyu Choi IEEE 2010 IEEE transactions on electron devices Vol.57 No.11
<P>Enhanced Dopant-segregated Schottky-barrier (DSSB) FinFETs combined with a fully silicided (FUSI) gate were fabricated via single-step Ni-silicidation. Both workfunction control of the gate and a lowered effective SB-height in the source/drain junctions are simultaneously achieved by the dopant-segregated silicidation process. Moreover, the leakage current was significantly reduced with the aid of deep source/drain implantation. Therefore, it can be expected that a DSSB device with a FUSI gate have several advantages as both a logic and nonvolatile memory device. First, for a logic device, it can provide low parasitic resistance and a tunable threshold voltage. Second, for a nonvolatile memory device, the increased workfunction due to the FUSI gate can enhance the erasing characteristics by suppressing the back tunneling of electrons from the gate side as well as the programming characteristics.</P>