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Yudai WAKAMOTO,Shinobu NAGAYAMA,Masato INAGI,Shin’ichi WAKABAYASHI 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
This paper presents design methods for (real-valued) discrete function generators using piecewise polynomial approximations, which are targeted for FPGA implementation. To approximate a given discrete function by polynomials efficiently, we propose three approximation algorithms based on spline functions. The proposed algorithms can significantly reduce memory size needed to implement a discrete function on an FPGA by accepting a small error, and can be used to explore design space taking into account a trade-off between memory size and approximation error. Experimental results show that the proposed algorithms reduce about 80% of memory size without losing speed of circuits by accepting only 1% approximation error, and the circuits designed by the proposed methods achieve about 75 times greater throughput than their software programs.
A Parallel Simulated Annealing Algorithm for LSI Floorplanning Running on Multicore Processors
Tomoaki SATO,Masato INAGI,Shinobu NAGAYAMA,Shin’ichi WAKABAYASHI 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
This paper proposes a new parallel simulated annealing (SA) suitable to multicore processors, in which multi-start approach and parallel local search were integrated in a sophisticated manner. The proposed parallel SA was applied to the LSI floorplanning problem. Experimental results showed that the proposed SA can produce floorplans comparable with ones obtained by the ordinary sequential SA, achieving more than 50% reduction of exectution time.
Efficient FPGA-based Hardware Algorithms for Approximate String Matching
Sadatoshi MIKAMI,Yosuke KAWANAKA,Shin’ichi WAKABAYASHI,Shinobu NAGAYAMA 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
In this paper, an efficient FPGA-based hardware algorithm and its extensions are proposed for calculating the edit distance as a degree of similarity between two strings. The proposed algorithms are implemented on FPGA and compared to software programs. Experimental results show the effectiveness of the proposed algorithms.