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FPGA Implementation of ATM Adaptation Layer for HDTV TS Communication over ATM Network
Jong Ick Lee,손종무,Seung ll Sonh,Hyeok Koo Jung,Moon Key Lee 에스케이텔레콤 (주) 2000 Telecommunications Review Vol.10 No.5
For the reduction of the jitter originated from the cell losses in ATM network when CBR traffic is transferred on AAL5, we propose that the receiver maintain a timer whose expiration time is proportional to the cell time of the source traffic plus the standard deviation of the 1-point CDV of the received ATM cells. Moreover, to enhance the granularity of the error or loss detection mechanism in the AAL5 PDUs, we also modified the AAL5 PDU trailer fields so that each cell comprising the AAL5 PDU has a sequence number field. The simulation results show that the peak-to-peak PDV of the AAL5 PDU by the proposed method is less than 69.4% to that by AAL5. Moreover, the AAL5 user - HDTV decoder - receives the same or more error-free transport packets in the proposed algorithm than those in the ITU-T AAL5 for the same network simulation environment. The proposed AAL is implemented in FPGA with operation frequency of 10MHz. The implemented system fully supports the HDTV system interface which operates at 2.42365MHz.