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- 저자 : Saegn-SUb Song (검색결과 2 건)
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Dae-Hyun Kim,Seong-Jin Yeon,Saegn-SUb Song,Jae-Hak Lee,Kwang-Seok Seo 대한전자공학회 2004 Journal of semiconductor technology and science Vol.4 No.2
A 30 nm In0.7GaAs High Electron Mobility Transistor (HEMT) with triple-gate has been successfully fabricated using the SiO₂/SiN, sidewall process and BCB planarization. The sidewall gate process was used to obtain finer lines, and the width of the initial line could be lessened to half by this process. To till the Schottky metal effectively to a narrow gate line after applying the developed sidewall process, the sputtered tungsten (W) metal was utilized instead of conventional e-beam evaporated metal. To reduce the parasitic capacitance through dielectric layers and the gate metal resistance (Rg), the etchedback BCB with a low dielectric constant was used as the supporting layer of a wide gate head, which also offered extremely low Rg of 1.7 Ohm for a total gate width (Wg) of 2X100 m. The fabricated 30nm In0.7GaAs HEMTs showed Vth of -0.4V, Gm,max, of 1.7S/mm, and f.r of 421GHz. These results indicate that InGaAs nano-HEMT with excellent device performance could be successfully fabricated through a reproducible and damage-free sidewall process without the aid of state-of-the-art lithography equipment. We also believe that the developed process will be directly applicable to the fabrication of deep sub-50nm InGaAs HEMTs if the initial line length can be reduced to below 50nm order.<br/> <br/>
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Kim, Dae-Hyun,Yeon, Seong-Jin,Song, Saegn-Sub,Lee, Jae-Hak,Seo, Kwang-Seok The Institute of Electronics and Information Engin 2004 Journal of semiconductor technology and science Vol.4 No.2
A 30 nm $In_{0.7}GaAs$ High Electron Mobility Transistor (HEMT) with triple-gate has been successfully fabricated using the $SiO_2/SiN_x$ sidewall process and BCB planarization. The sidewall gate process was used to obtain finer lines, and the width of the initial line could be lessened to half by this process. To fill the Schottky metal effectively to a narrow gate line after applying the developed sidewall process, the sputtered tungsten (W) metal was utilized instead of conventional e-beam evaporated metal. To reduce the parasitic capacitance through dielectric layers and the gate metal resistance ($R_g$), the etchedback BCB with a low dielectric constant was used as the supporting layer of a wide gate head, which also offered extremely low Rg of 1.7 Ohm for a total gate width ($W_g$) of 2x100m. The fabricated 30nm $In_{0.7}GaAs$ HEMTs showed $V_{th}$of -0.4V, $G_{m,max}$ of 1.7S/mm, and $f_T$ of 421GHz. These results indicate that InGaAs nano-HEMT with excellent device performance could be successfully fabricated through a reproducible and damage-free sidewall process without the aid of state-of-the-art lithography equipment. We also believe that the developed process will be directly applicable to the fabrication of deep sub-50nm InGaAs HEMTs if the initial line length can be reduced to below 50nm order.
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