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다문화 청소년 국악인식개선을 위한 교내 국악방송 프로그램 개발 연구 : PBL(문제중심학습)을 중심으로 = Research on the Development of School Korean Classical Music Broadcasting Program for Improving Multi-Culture Students' Recognition of Korean Classical Music : Based on PBL(Problem Based Learning)
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Piezo圧電 結晶体에서의 表面弹性波 增幅에 関한 研究
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기형도 시의 물 이미지 연구 = A Study on Water Images of Ki Hyung-do's Poetry
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한강과 페퇴츠 언드라쉬의 소설에 나타나는 생태비평 비교 연구:
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Chariots of the Gods? : Unsolved mysteries of the past
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디지털 방송 서비스를 위한 시스템 구조 연구
- 검색키워드
- 저자 : Sabooh Ajaz (검색결과 5 건)
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Pipeline-Aware QC-IRA-LDPC Code and Efficient Decoder Architecture
Sabooh Ajaz(사부흐),Hanho Lee(이한호) 대한전자공학회 2014 전자공학회논문지 Vol.51 No.10
본 논문은 PIPELINE-AWARE QC-IRA-LDPC (PA-QC-IRA-LDPC) 코드 생성 방법과 Rate-1/2 (2016,1008) PA-QC-IRA-LDPC 코드에 대한 효율적인 고속 복호기 구조를 제안한다. 제안한 방법은 비트 오류율 (BER) 성능 저하 없이 파이프라인 기법을 사용하여 임계경로를 나눌 수 있다. 또한 제안한 복호기 구조는 데이터 처리량, 하드웨어 효율 및 에너지 효율을 크게 향상시킬 수 있다. 제안한 복호기 구조는 90-nm CMOS 기술을 사용하여 합성 및 레이아웃이 수행되었으며, 이전에 보고된 복호기 구조들에 비해서 하드웨어 효율성이 53%이상 향상되었고, 훨씬 좋은 에너지 효율성을 보여준다. This paper presents a method for constructing a pipeline-aware quasi-cyclic irregular repeat accumulate low-density parity-check (PA-QC-IRA-LDPC) codes and efficient rate-1/2 (2016, 1008) PA-QC-IRA-LDPC decoder architecture. A novel pipeline scheduling method is proposed. The proposed methods efficiently reduce the critical path using pipeline without any bit error rate (BER) degradation. The proposed pipeline-aware LDPC decoder provides a significant improvement in terms of throughput, hardware efficiency, and energy efficiency. Synthesis and layout of the proposed architecture is performed using 90-nm CMOS standard cell technology. The proposed architecture shows more than 53% improvement of area efficiency and much better energy efficiency compared to the previously reported architectures.
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An Area-efficient Half-row Pipelined Layered LDPC Decoder Architecture
Sabooh Ajaz,Tram Thi Bao Nguyen,Hanho Lee 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.6
This paper presents an area-efficient half-row pipelined layered low-density parity check (LDPC) decoder architecture for IEEE 802.11ad applications. The proposed decoder achieves a good tradeoff between throughput and area because of its ability to overcome the low-throughput bottleneck in conventional half-row decoders and the high-complexity bottleneck in fully parallel decoders. Synthesis results using TSMC 40 nm CMOS technology shows much better throughput at 10.84 Gbps and superior area efficiency, compared to previously reported LDPC decoders.
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Kim, Cheolho,Yun, Haram,Ajaz, Sabooh,Lee, Hanho The Institute of Electronics and Information Engin 2015 Journal of semiconductor technology and science Vol.15 No.3
This paper presents a high-throughput low-complexity decoder architecture and design technique to implement successive-cancellation (SC) polar decoding. A novel merged processing element with a one's complement scheme, a main frame with optimal internal word length, and optimized feedback part architecture are proposed. Generally, a polar decoder uses a two's complement scheme in merged processing elements, in which a conversion between two's complement and sign-magnitude requires an adder. However, the novel merged processing elements do not require an adder. Moreover, in order to reduce hardware complexity, optimized main frame and feedback part approaches are also presented. A (1024, 512) SC polar decoder was designed and implemented using 40-nm CMOS standard cell technology. Synthesis results show that the proposed SC polar decoder can lead to a 13% reduction in hardware complexity and a higher clock speed compared to conventional decoders.
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Cheolho Kim,Haram Yun,Sabooh Ajaz,Hanho Lee 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.3
This paper presents a high-throughput lowcomplexity decoder architecture and design technique to implement successive-cancellation (SC) polar decoding. A novel merged processing element with a one’s complement scheme, a main frame with optimal internal word length, and optimized feedback part architecture are proposed. Generally, a polar decoder uses a two’s complement scheme in merged processing elements, in which a conversion between two’s complement and sign-magnitude requires an adder. However, the novel merged processing elements do not require an adder. Moreover, in order to reduce hardware complexity, optimized main frame and feedback part approaches are also presented. A (1024, 512) SC polar decoder was designed and implemented using 40-nm CMOS standard cell technology. Synthesis results show that the proposed SC polar decoder can lead to a 13% reduction in hardware complexity and a higher clock speed compared to conventional decoders.
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멀티-기가비트 WPAN 시스템을 위한 고속 QC-LDPC 복호기 구조
이한호(Hanho Lee),사부흐(Sabooh Ajaz) 대한전자공학회 2013 전자공학회논문지 Vol.50 No.2
60GHz 멀티-기가비트 WPAN 시스템을 위한 고속 QC-LDPC 복호기의 구조를 제안한다. 제안한 QC-LDPC 복호기 설계를 위하여 4 블록-병렬 계층 복호 기술과 fixed wire network 기술이 적용 되었다. 2단 파이프라이닝과 4 블록-병렬 계층 복호기술은 동작 주파수와 데이터 처리량을 개선시키는데에 큰 효과가 있다. 또한 본 제안한 복호기 구조에서 스위치 네트워크를 구현하여 위하여 fixed wire network로 간단하게 구현될 수 있으면 하드웨어 복잡도를 크게 감소시킬 수 있다. 제안한 672-비트, rate-1/2인 QC-LDPC 복호기 구조는 90-nm CMOS 표준 셀을 이용해 설계 및 합성하였다. 성능 분석 결과 제안한 QC-LDPC 복호기 구조는 794K 게이트를 가지며 클락 속도 290MHz 에서 작동한다. 12-iteration일 때 데이터 처리율은 3.9Gbps 이며 60GHz WPAN 시스템에 적용되어 사용 될 수 있다. A high-throughput Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture is proposed for 60GHz multi-gigabit wireless personal area network (WPAN) applications. Two novel techniques which can apply to our selected QC-LDPC code are proposed, including a four block-parallel layered decoding technique and fixed wire network. Two-stage pipelining and four block-parallel layered decoding techniques are used to improve the clock speed and decoding throughput. Also, the fixed wire network is proposed to simplify the switch network. A 672-bit, rate-1/2 QC-LDPC decoder architecture has been designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed QC-LDPC decoder requires a 794K gate and can operate at 290 MHz to achieve a data throughput of 3.9 Gbps with a maximum of 12 iterations, which meet the requirement of 60 GHz WPAN applications.
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