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A Low-Jitter Area-Efficient LC-VCO Based Clock Generator in 0.13-µm CMOS
LEE, Joonhee,KIM, Sungjun,JEON, Sehyung,LEE, Woojae,CHO, SeongHwan The Institute of Electronics, Information and Comm 2009 IEICE transactions on electronics Vol.92 No.4
<P>This letter presents an ultra low-jitter clock generator that employs an area-efficient LC-VCO. In order to fully utilize the area of the on-chip inductor, the loop filter of a phase locked loop (PLL) is located underneath the inductor. A prototype chip implemented in 0.13µm CMOS process achieves 105MHz to 225MHz of clock frequency while consuming 4.2mW from 1.2V supply. The measured rms jitter and normalized rms jitter of the proposed clock generator are 2.8ps and 0.031% at 105MHz, respectively.</P>
An Ultra-High Input Impedance Analog Front End Using Self-Calibrated Positive Feedback
Lee, Jinseok,Lee, Geon-Hwi,Kim, Hyojun,Cho, SeongHwan IEEE 2018 IEEE journal of solid-state circuits Vol.53 No.8
<P>This paper presents circuit techniques for ultra-high input impedance analog front end (AFE). In order to boost input impedance, various on- and off-chip parasitic capacitances are cancelled using an active shield and negative capacitance technique. To maximize the cancellation, a self-calibration scheme with active shield replica is proposed for positive feedback-based negative capacitance, which settles at the boundary between stable and unstable states in calibration mode. A prototype IC fabricated in 0.18- <TEX>$\mu \text{m}$</TEX> CMOS achieves an input impedance of 50 <TEX>$\text{G}\Omega$</TEX> at 50 Hz, equivalent to 60-fF capacitance, while consuming 289 nW from 0.8-V supply. The proposed AFE is applied to heart-rate monitoring using 1-cm<SUP>2</SUP> dry electrodes over clothes without any straps.</P>
Jaewon Lee,Woojae Lee,SeongHwan Cho IEEE 2012 IEEE journal on emerging and selected topics in ci Vol.2 No.2
<P>In this paper, a high-frequency crosstalk compensation scheme for high speed multi-channel on-chip interconnect is proposed. In the proposed scheme, a zero is inserted to the aggressor branch of the crosstalk feed-forward equalizer, which compensates for the high-frequency crosstalk, resulting in reduced timing jitter and increased eye opening. In order to verify the proposed scheme, an eight-channel 10-mm on-chip interconnect is implemented in 130-nm CMOS process. Measurement results show that the proposed scheme effectively removes the high frequency crosstalk and achieves a data rate of 2.9 Gb/s at a bit-error-rate below . The power consumption of the proposed transceiver is about 1 mW which corresponds to an energy efficiency of 0.4 pJ/bit.</P>
허성환(Seonghwan Heo),이원기(Wonkee Lee),이종혁(Jonghyeok Lee) 한국정보과학회 2021 한국정보과학회 학술발표논문집 Vol.2021 No.6
목적 지향 대화 시스템(task-oriented dialogue system)의 한 가지 중요한 구성 요소인 발화 이해(Spoken Language Understanding, SLU)는 사용자 발화의 의도(intent)와 의미적 슬롯(semantic slot)을 찾는 것을 목표로 한다. 본 연구에서는 의미적 슬롯을 찾아내는 슬롯 채우기(slot filling)문제를 해결하는 데 있어, 학습 데이터의 부족 문제를 지적하고, 이러한 문제를 해결하기 위해 크로스도메인 슬롯 채우기(cross-domain slot filling) 방법을 통해 접근한다. 본 연구에서는 이전까지 적용되지 않았던 사전학습 언어 모델인 BERT를 크로스도메인 슬롯 채우기에 적용하였고, 기존의 연구와 비교하여 그 성능이 향상됨을 확인하였다.
A 2.5-Gb/s On-Chip Interconnect Transceiver With Crosstalk and ISI Equalizer in 130 nm CMOS
Jaewon Lee,Woojae Lee,SeongHwan Cho IEEE 2012 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 1 R Vol.59 No.1
<P>In this paper, a crosstalk compensation scheme for high speed single-ended on-chip signaling is presented. To reduce the effect of crosstalk in bandwidth enhanced channel employing capacitively driven interconnect, a crosstalk feed-forward equalizer is proposed, which compensates for the low-pass nature of the crosstalk. The proposed scheme is verified using a three-channel 10 mm on-chip interconnect implemented in 130 nm CMOS process. Measurement results show that the proposed transceiver effectively removes the crosstalk for data rates of up to 2.5-Gb/s while consuming 0.96 mW, which corresponds to energy efficiency of 0.41 pJ/bit.</P>
Undeflatable balloon guide catheter (BGC) during endovascular procedure: Rescue strategy
Hyungkyu Lee,Taejoon Park,Jinwook Baek,Seonghwan Kim,Sang Pyung Lee,Kyoungsoo Ryou 대한뇌혈관외과학회 2022 Journal of Cerebrovascular and Endovascular Neuros Vol.24 No.4
The use of a balloon guide catheter (BGC) in the endovascular management of acute ischemic stroke is known to improve the efficacy and efficiency of the procedure by reducing the risk of distal embolization. During the procedure, the balloon of the catheter causes a temporary arrest of cerebral blood flow. However, failure of the balloon to deflate during the BGC procedure can result in catastrophic complications, including aggravated hypoxic damage. This paper aims to share the resolution and methodological analysis of our experience with BGC balloon deflation failure, which was confirmed by a reproducible experiment under similar conditions.