RISS 학술연구정보서비스

검색
다국어 입력

http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.

변환된 중국어를 복사하여 사용하시면 됩니다.

예시)
  • 中文 을 입력하시려면 zhongwen을 입력하시고 space를누르시면됩니다.
  • 北京 을 입력하시려면 beijing을 입력하시고 space를 누르시면 됩니다.
닫기
    인기검색어 순위 펼치기

    RISS 인기검색어

      검색결과 좁혀 보기

      선택해제

      오늘 본 자료

      • 오늘 본 자료가 없습니다.
      더보기
      • 무료
      • 기관 내 무료
      • 유료
      • KCI등재

        Dimensional Effect on Analog/RF Performance of Dual Material Gate Junctionless FinFET at 7 nm Technology Node

        Rambabu Kusuma,V. K. Hanumantha Rao Talari 한국전기전자재료학회 2023 Transactions on Electrical and Electronic Material Vol.24 No.3

        Fully Depleted Silicon On Insulator (FDSOI) structures are present-era technology as it has enhanced control over Short Channel Effects in the sub-nanometre regime. This paper studies the analog and radio frequency performance of junctionless FinFET with dual material gate (DMG JLFinFET) based on FDSOI for low power applications. We extracted analog and radio frequency parameters with the variation of fin height (FH = 10 nm to 30 nm) and fin width (FW = 46 nm). The parameters like transconductance (gm), transconductance generation factor, cut-off frequency (fT), intrinsic delay (τ), gate capacitance (Cgg), gate to source capacitance (Cgs), gate to drain capacitance (Cgd), and transconductance frequency product, gain bandwidth product are calculated. At FH = 6 nm all the parameters are increased except time delay which was small decrement. Similarly for FW also all the parameters are improved with increment of fin width except time delay. In contempt Cgd and Cgg are less impact on dimensional variation. From this study it reveals that, in FinFET design, designers have to consider dimensional variations in Anlog/RF parameters and FinFET is suitable candidate for nano scale low power Anlog/RF applications. In this work all these simulations are carried out by Cogenda Visual TCAD.

      연관 검색어 추천

      이 검색어로 많이 본 자료

      활용도 높은 자료

      해외이동버튼