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A Verifiable Design Methodology at System-Level
Camurati, P.,Como, F.,Prinetto, P.,Bayol, C.,Soulas, B. 대한전자공학회 1993 ICVC : International Conference on VLSI and CAD Vol.3 No.1
Working at system level is attracting increasing interest, as it supports the exploration of several alternatives, before the hardwarelsoftware partitioning takes place. New issues must be taken into account, such as validation and verification at alt steps. This paper presents a system-level design methodology that supports verification. Starting from a description in a verification-oriented version of VHDL, art efficient BDD-based tool for Process Algebras is used to perform equivalence proofs.