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Review of alternative gate stack technology research during the last decade
Byoung Hun Lee1,Paul Kirsch,Husam Alshareef,Prashant Majhi,Rino Choi,Seungchul Song,Hsing Huang Tseng,Raj Jammy 한국세라믹학회 2006 세라미스트 Vol.9 No.4
Scaling of the gate stack has been one of the major contributors to the performance enhancement of CMOSFET devices in past technology generations The scalability of gate stack has diminished in recent years and alternative gate stack technology such as metal electrode and high-k dielectrics has been intensively studied during almost matches that of conventional SiO2-based gate dielectrics. However, many technical challenges remain to be resolved before alternative gate stacks can be introduced into mainstream technology. This paper reviews the reasearch in alternative gate stack technologies to provide insights for future reasearch.
Jinwoo Noh,Minseok Jo,Chang Yong Kang,Gilmer, David,Kirsch, Paul,Lee, Jack C.,Byoung Hun Lee IEEE 2013 IEEE electron device letters Vol.34 No.9
<P>A semiempirical model that can simulate dc and pulse (ac) characteristics of filament-type HfO<SUB>x</SUB>-based resistance change random access memory (ReRAM) devices has been developed. Time-dependent device characteristics, because of the dynamic change in the filament size, were emulated using a modified ion migration model. This model describes the difference between SET and RESET operations using a current crowding effect This model is a semiempirical model that can simultaneously match both dc and ac characteristics of HfOx-based ReRAM devices.</P>
OH, Jungwoo,HUANG, Jeff,OK, Injo,LEE, Se-Hoon,D. KIRSCH, Paul,JAMMY, Raj,LEE, Hi-Deok The Institute of Electronics, Information and Comm 2011 IEICE transactions on electronics Vol.94e.c No.5
<P>We have demonstrated high mobility MOS transistors on high quality epitaxial SiGe films selectively grown on Si (100) substrates. The hole mobility enhancement afforded intrinsically by the SiGe channel (60%) is further increased by an optimized Si cap (40%) process, resulting in a combined ∼100% enhancement over Si channels. Surface orientation, channel direction, and uniaxial strain technologies for SiGe channels CMOS further enhance transistor performances. On a (110) surface, the hole mobility of SiGe pMOS is greater on a (110) surface than on a (100) surface. Both electron and hole mobility on SiGe (110) surfaces are further enhanced in a <110> channel direction with appropriate uniaxial channel strain. We finally address low drive current issue of Ge-based nMOSFET. The poor electron transport property is primarily attributed to the intrinsically low density of state and high conductivity effective masses. Results are supported by interface trap density (D<SUB>it</SUB>) and specific contact resistivity (<I>ρ<SUB>c</SUB></I>).</P>