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Joint Japan-Korea HDR Satellite Communication Experiment Phase II
Nishinaga, Nozomu,Takahashi, Takashi,Tanaka, Masato,Jang, Jae-Hyeuk 통신위성우주산업연구회 2001 Joint Conference on Satellite Communications Vol.2001 No.-
Satellite communications has characteristics such as the wide area coverage and the flexibility of the network construction. Especially, a communication system with geostationary satellite is easy to be tracked and can establish the broadband communication network. Therefore, it is expected that Internet operable, broadband and wide area coverage IP satellite network can be established. Communications Research Laboratory (CRL) is promoting the technology development to utilize a satellite communications system as the solution of the wide area communication network construction and the international High Data Rate (HDR) satellite communications experiment to demonstrate application operability. We have succeeded Joint Japan-Korea HDR Satellite Communication Experiment Phase 1.In this paper, we report some results of domestic experiment that has carried out as preliminary next phase experiment in summer and propose next phase's experiment items and network configuration.
Reconfigurable Communication Satellite System "SoftSAT"
Nishinaga, Nozomu,Ogawa, Yasuo,Takayama, Yoshihisa,Takahashi, Takashi,Kubooka, Toshihiro,Hiroaki, Umehara Hanako 통신위성우주산업연구회 2002 Joint Conference on Satellite Communications Vol.2002 No.-
Satellite communications provides characteristics such as wide-area coverage and flexibility of network construction. Since an enormous budget and time are require for satellite development, however, it is difficult to implement the latest techniques onboard. Even of the latest communications technology is implemented at the time of launch, it is impossible to follow paradigm shifts in terrestrial network technology. In this paper, we propose a reconfigurable communication satellite system based on the formation-flight technique and inter-satellite communication technology. This satellite system consists of a group of layered satellites that can operate together like one satellite.
Yasuhiro NISHINAGA,Takuro UCHIDA,Tetsuya ZUYAMA,Kazuya TANIGAWA,Tetsuo HIRONAKA 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
We have developed the dynamic reconfigurable processor DS-HIE for the streaming processing in our laboratory. The software development environment for the DS-HIE processor was not developed. So it is difficult to evaluate the performance of the DS-HIE processor by using practical applications. Therefore, this paper explains about the development of the compiler for the DS-HIE processor, which supports high-level programming language. The compiler consists of the Front-end part and the Back-end part. Since it will take time to develop a high quality Front-end from the scratch, so we selected the COINS compiler as the Front-end compiler. The Back-end compiler extracts the parts executed by the DS-HIE processor in the input program, and then maps the operations to the Function Units in the DS-HIE processor. After that, the Back-end compiler routes wires between the Function Units. The applications to evaluate the compiler were one dimensional DCT and row processing of LDCP decoding. As a compilation result, the average usage of the function unit was 83%
Development of Heterogenous Multi-core Processor ”Hy-DiSC” with Dynamic Reconfigurable Processor
Takuro UCHIDA,Yasuhiro NISHINAGA,Tetsuya ZUYAMA,Kazuya TANIGAWA,Tetsuo HIRONAKA 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
For accelerating multimedia applications by streaming, we have proposed the heterogeneous multicore processor Hy-DiSC with dynamic reconfigurable processor DS-HIE. The goal of the Hy-DiSC processor is to achieve high performance in a small chip area. In this paper, the performance improvement of the Hy-DiSC processor adopting the DS-HIE processor was evaluated. The application programs that selected for performance evaluation was a JPEG encoding process and the 2-D DCT included in the JPEG encoding process. And, the DS-HIE processor accelerates the 2-D DCT included in the JPEG encoding process. As a result, compared with the MeP processor the DS-HIE processor achieved 28 times higher performance on the execution of 2-D DCT. And, the DS-HIE processor requires fewer transistor counts to implement it.
Toward future networks: A viewpoint from ITU-T
Matsubara, D.,Egawa, T.,Nishinaga, N.,Kafle, V. P.,Myung-Ki Shin,Galis, A. IEEE 2013 IEEE communications magazine Vol.51 No.3
<P>There have been continuous efforts and progress regarding the research and development of future network technologies in recent years, such as network virtualization and software defined networking, information centric networking (ICN), cloud networking, autonomic management, and open connectivity. ITU-T started working on the standardization of FNs in late 2009, and it has developed some initial Recommendations that lay out the essential directions for subsequent detailed work. This article presents the background and the context of FNs' standardization, and the deliverables and future plans originated from the initial standardization work performed by ITU-T.</P>