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Naohiro Hamada,Hiroshi Saito 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
This paper proposes an iterative method of behavioral synthesis and floorplanning for asynchronous circuits with bundled-data implementation. The proposed method estimates the delay of operations from the result of floorplanning to synthesize a Register Transfer Level (RTL) model. Experimental results show that the proposed method synthesizes superior circuits in performance compared to the synchronous counterparts with accurate delay estimation.