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A Reconfigurable Design of Lattice Cryptographic Functional Server Farms
Sangook Moon 한국정보통신학회 2015 2016 INTERNATIONAL CONFERENCE Vol.7 No.1
Due to advances in chip technology, the complexity of hardware and software comprising embedded systems is facing its limitations. Therefore, it is getting hard to design complex designs only with conventional methods. In this paper, we introduce a new method of building reconfigurable designs with a derivation of SystemVerilog. We apply the concept of object oriented implementation of the SystemVerilog to the design of arithmetic functional server farms. We successfully implemented a prototype system with a floating point functional engines and the test bench in one integrated environment. Conventional approach with Verilog/VHDL with C/SystemC verification would have cost significant more time and effort.
Moon, Sangook,Park, Jongsu Hindawi Limited 2014 Journal of applied mathematics (JAM) Vol.2014 No.-
<P>As today’s hardware architecture becomes more and more complicated, it is getting harder to modify or improve the microarchitecture of a design in register transfer level (RTL). Consequently, traditional methods we have used to develop a design are not capable of coping with complex designs. In this paper, we suggest a way of designing complex digital logic circuits with a soft and advanced type of SystemVerilog at an electronic system level. We apply the concept of design-and-reuse with a high level of abstraction to implement elliptic curve crypto-processor server farms. With the concept of the superior level of abstraction to the RTL used with the traditional HDL design, we successfully achieved the soft implementation of the crypto-processor server farms as well as robust test bench code with trivial effort in the same simulation environment. Otherwise, it could have required error-prone Verilog simulations for the hardware IPs and other time-consuming jobs such as C/SystemC verification for the software, sacrificing more time and effort. In the design of the elliptic curve cryptography processor engine, we propose a 3X faster GF(2<SUP><I>m</I></SUP>) serial multiplication architecture.</P>
Memory Saving Architecture of Number Theoretic Transform for Lattice Cryptography
Sangook Moon 보안공학연구지원센터 2016 International Journal of Security and Its Applicat Vol.10 No.9
In realizing a homomorphic encryption system, the operations of 1encrypt, decrypt, and recrypt constitute major portions. The most important common operation for each back-bone operations include a polynomial modulo multiplication for over million-bit integers, which can be obtained by performing integer Fourier transform, also known as number theoretic transform. In this paper, we adopt and modify an algorithm for calculating big integer multiplications introduced by Schonhage-Strassen to propose an efficient Ring-LWE processor architecture which can save memory. The proposed architecture of Ring-LWE encryption processor has been implemented on an FPGA and evaluated.