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Fault Analysis of Interconnect Opens in 90nm CMOS ICs with Device Simulator
Masaki Hashizume,Yuichi Yamada,Hiroyuki Yotsuyanagi,Toshiyuki Tsutsumi,Koji Yamazaki,Yoshinobu Higami,Hiroshi Takahashi,Yuzo Takamatsu 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
In this paper, faulty effects of interconnect opens in logic ICs fabricated with a 90㎚ CMOS process are analyzed by device simulation. In the analysis, it is examined whether a logical error can be caused at an opened input signal line by logic signals of the neighboring signal lines. The simulation results suggest us that a logical error may occur at an interconnect surrounding by 8 interconnects if the interconnects are longer than 5㎛ and the width of an open defect is greater than 2.0㎚.
Current Testable Design of Resistor String DACs for Short Defects
Masaki Hashizume,Yutaka Hata,Hiroyuki Yotsuyanagi,Yukiya Miura 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
In this paper, we propose a DFT method for resistor string DACs that enables us to test them easily by supply current test method. The targeted defects are shorts in the DACs. It is shown by some experiments that all of the targeted defects in a DAC designed with the DFT method can be detected with a smaller number of test vectors.
Current Testable Design of Resistor String DACs for Open Defects
Yutaka Hata,Masaki Hashizume,Hiroyuki Yotsuyanagi,Yukiya Miura 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
In this paper, a DFT method of resistor string digital-to-analog converters (DACs) is proposed so as to be tested fully by supply current testing. Targeted defects are opens in the DACs. Testability of opens in testable designed DACs is examined experimentally. The results show that all of the opens in an N-bits testable designed DAC will be detected with test vectors of about 2(N-1) by supply current testing.