http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
설계자동화를 위한 VHDL Analyzer에 관한 연구
印致虎 世明大學校 1992 世明論叢 Vol.2 No.-
This paper has developed the automation system for logic design, using widely available VHDL language as the standard hardware description language[1][8][9], which extracts the efficient FSM(Finite State Machine) List in automatic optimized synthesis for the practical ASIC hardware from the design technique of the register transfer level. VHDL analysis process in this paper is similar to compiler process in software area, is partitioned into the VHDL parsing, the Behavioral transformation, the Basic block recognition, and the Dependency analysis, etc[5][7]. VHDL parsing resulted in the FSM (Finite State Machine) List efficient in Data Path and Control Path synthesis for logic design with creating the intermediate code in AST(Abstract Syntax Tree) for the intermediate symbol table.
ASIC설계 자동화를 위한 새로운 최소자원 스케쥴링 알고리듬
인치호 世明大學校 1998 世明論叢 Vol.7 No.-
This thesis presents a new VHDL intermediate format CDFG(Control Data Flow Graph) an a new scheduling algorithm for an optimal control dominated ASIC design. The proposed CDFG is a control flow graph whcih represents conditional brances and loops efficiently. Also it represents ata dependency and such constraints as hardware resource and timing. In scheduling algorithm, the contraints are substituted by subgraphs, and then the number of subgraphs (that is the number of the constraints) is minimized by using the inclusion and overlap relation among subgraphs. The effectiveness of the proposed algorithm has been proven by the experiment with the bnchmark examples.
최지영,인치호 世明大學校 1998 世明論叢 Vol.7 No.-
This thesis proposes a new hardware allocation algorithm for design automation. The proposed algorithm works on scheduled input graph and simultaneously allocates binds functional units, interconnections and registers by considering interdependency between operations and storage elements in each control step, in order to share registers and interconnections connected to functional units, as much as possible. This thesis shows the effectiveness of the algorithm by comparing the results of our experiments with those of exiting system.
움직임 추정을 위한 시스톨릭 어레이를 사용한 효율적인 VLSI 구조
진용선,인치호 世明大學校 1997 世明論叢 Vol.6 No.-
In this paper. an efficient VLSI architecture for Full search Block Matchin Algorithm (FBMA) with systolic arrays is proposed. Because FBMA for motion estimation is simple, regular. and modular. its suitable for VlSI implementation with systolic arrays. Considering the data flow on overlapping search areas, which exist in both the same and perpendicular direction to searching course, the redundancy of duplicated data input for each reference block is removed to enhance the performance of FBMA.
A New Efficient High-Level Synthesis Methodology for Lower Power
Chi-Ho Lin 대한전자공학회 2008 ICEIC:International Conference on Electronics, Inf Vol.1 No.1
This paper presents a new efficient high-level synthesis methodology for low power design. In the scheduling technique, the constraints are substituted by subgraphs, and then the number of subgraphs is minimized by using the inclusion and overlap relation efficiently. Also, the register allocation algorithm determines the minimum register after the life-time analysis of all variable in allocation algorithm. It is a minimum the switching activity using graph coloring technique for low power consumption. And the supply voltage is reduced a maximal using multiple voltage considering resource constraints. The proposed algorithm proves the effect through various high-level synthesis benchmark to adopt a low power scheduling and allocation algorithm considering in multiple supply voltage.
A New Clock Skew Scheduling Methodology for High-Level Power Optimization
Chi-Ho Lin 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
In this paper, we present a new clock skew scheduling methodology for high-level power optimization to optimize the power consumption in the synthesized data path. In this paper, The proposed CDFG represents control flow, data dependency and such constraints as resource constraints and timing constraints. In the scheduling technique, the constraints are substituted by subgraphs, and then the number of subgraphs is minimized by using the inclusion and overlap relation efficiently. Also, we plans for the clock skew scheduling in physical design stages during register binding. At the same time it ensures not invalidating the subsequent clock skew scheduling for optimizing the clock period. We use the switching power as the native objective of our register binding problem. The effectiveness of the proposed algorithm has been proven by the experiment with the benchmark examples.
A New High-Level Power Optimization Methodology for Clock Period Minimization
Chi-Ho Lin 대한전자공학회 2007 ITC-CSCC :International Technical Conference on Ci Vol.2007 No.7
In this paper, we present a new high-level power optimization methodology for clock period minimization that can be used to optimize the power consumption in the synthesized data path.. This paper is the first attempt to the high-level synthesis of non-zero clock skew designs. First, we show that the register binding in high-level synthesis stage has a significant impact on the clocking constraints between registers. As a result, different register binding solutions lead to different smallest feasible clock periods. Then, based on that observation, we formulate the problem of register binding for clock period minimization. Given a constraint on the number of registers, our objective is to find a minimum period register binding solution. The effectiveness of the proposed algorithm has been proven by the experiment with the benchmark examples.
A High-Level Power Estimation Methodology for Low Power Design
Chi-Ho Lin 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
This work is a contribution to high-level synthesis for low power systems. In this paper, we present an efficient algorithm on performing estimation with an aim of reducing the power consumption in the synthesized data path. In this paper, CDFG represents control flow, data dependency and such constraints as resource constraints and timing constraints. In the scheduling technique, the constraints are substituted by subgraphs, and then the number of subgraphs is minimized by using the inclusion and overlap relation efficiently. Also, The power estimation methods on enable power management and module selection are performed, so as to reduce the power consumption in low power design. The effectiveness of the proposed algorithm has been proven by the experiment with the benchmark examples.