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A 1.62/2.7Gbps clock and data recovery with pattern based frequency detector for displayport
Kyungyoul Min,Changsik Yoo IEEE 2010 IEEE transactions on consumer electronics Vol.56 No.4
<P>A clock and data recovery (CDR) for the physical layer of DisplayPort at sink side is described. A 1/5-rate linear phase detector (PD) compares the phase of the incoming data with that of sampling clock to recover a clean clock and data. A pattern based frequency detector (PBFD) reduces frequency error to be in the pullin-range of the 1/5-rate linear PD. The PBFD reduces the frequency error down to 3.2% before the linear PD starts its operation. The CDR implemented in a 0.13 m CMOS process shows 29-ps rms and 154-ps peak-to-peak jitter in the recovered clock and 10<SUP>-7</SUP> bit error rate (BER) for 2<SUP>31</SUP>-1 pseudorandom binary-sequence (PRBS) input while consuming 87mW from a 1.2-V supply.</P>
An Offset-Compensated LVDS Receiver with Low-Temperature Poly-Si Thin Film Transistor
Kyungyoul Min,유창식 한국전자통신연구원 2007 ETRI Journal Vol.29 No.1
The poly-Si thin film transistor (TFT) shows large variations in its characteristics due to the grain boundary of poly-crystalline silicon. This results in unacceptably large input offset of low-voltage differential signaling (LVDS) receivers. To cancel the large input offset of poly- Si TFT LVDS receivers, a full-digital offset compensation scheme has been developed and verified to be able to keep the input offset under 15 mV which is sufficiently small for LVDS signal receiving.