Application-aware Design Parameter Exploration of NAND Flash Memory

Kwanhu Bang,Dong-Gun Kim,Sang-Hoon Park,Eui-Young Chung,Hyuk-Jun Lee 대한전자공학회 2013 Journal of semiconductor technology and science Vol.13 No.4

NAND flash memory (NFM) based storage devices, e.g. Solid State Drive (SSD), are rapidly replacing conventional storage devices, e.g. Hard Disk Drive (HDD). As NAND flash memory technology advances, its specification has evolved to support denser cells and larger pages and blocks. However, efforts to fully understand their impacts on design objectives such as performance, power, and cost for various applications are often neglected. Our research shows this recent trend can adversely affect the design objectives depending on the characteristics of applications. Past works mostly focused on improving the specific design objectives of NFM based systems via various architectural solution when the specification of NFM is given. Several other works attempted to model and characterize NFM but did not access the system-level impacts of individual parameters. To the best of our knowledge, this paper is the first work that considers the specification of NFM as the design parameters of NAND flash storage devices (NFSDs) and analyzes the characteristics of various synthesized and real traces and their interaction with design parameters. Our research show that optimizing design parameters depends heavily on the characteristics of applications. The main contribution of this research is to understand the effects of low-level specifications of NFM, e.g. cell type, page size, and block size, on system-level metrics such as performance, cost, and power consumption in various applications with different characteristics, e.g. request length, update ratios, read-and-modify rations. Experimental results show that the optimized page and block size can achieve up to 15 times better performance than the conventional NFM configuration in various applications. The results can be used to optimize the system-level objectives of a system with specific applications, e.g. embedded systems with NFM chips, or predict the future direction of NFM.

Extended MPEG Video Format for Efficient Dynamic Voltage Scaling

BANG, Kwanhu,BANG, Sung-Yong,CHUNG, Eui-Young The Institute of Electronics, Information and Comm 2008 IEICE transactions on fundamentals of electronics, Vol.91 No.5

<P>We present an extended MPEG video format for efficient Dynamic Voltage Scaling (DVS). DVS technique has been widely researched, but the execution time variation of a periodic task (i. e. MPEG decoding) is still a challenge to be tackled. Unlike previous works, we focus on the data (video stream) rather than the execution code to overcome such limitation. The proposed video format provides the decoding costs of frames to help the precise prediction of their execution times at client machines. The experimental results show that the extended format only increases the data size less than 1% by adding about 10bits representing the decoding cost of each frame. Also, a DVS technique adjusted for the proposed format achieves 90% of efficiency compared to the oracle case, while keeping the run time overhead of the technique negligible.</P>

Application-aware Design Parameter Exploration of NAND Flash Memory

Bang, Kwanhu,Kim, Dong-Gun,Park, Sang-Hoon,Chung, Eui-Young,Lee, Hyuk-Jun The Institute of Electronics and Information Engin 2013 Journal of semiconductor technology and science Vol.13 No.4

NAND flash memory (NFM) based storage devices, e.g. Solid State Drive (SSD), are rapidly replacing conventional storage devices, e.g. Hard Disk Drive (HDD). As NAND flash memory technology advances, its specification has evolved to support denser cells and larger pages and blocks. However, efforts to fully understand their impacts on design objectives such as performance, power, and cost for various applications are often neglected. Our research shows this recent trend can adversely affect the design objectives depending on the characteristics of applications. Past works mostly focused on improving the specific design objectives of NFM based systems via various architectural solutions when the specification of NFM is given. Several other works attempted to model and characterize NFM but did not access the system-level impacts of individual parameters. To the best of our knowledge, this paper is the first work that considers the specification of NFM as the design parameters of NAND flash storage devices (NFSDs) and analyzes the characteristics of various synthesized and real traces and their interaction with design parameters. Our research shows that optimizing design parameters depends heavily on the characteristics of applications. The main contribution of this research is to understand the effects of low-level specifications of NFM, e.g. cell type, page size, and block size, on system-level metrics such as performance, cost, and power consumption in various applications with different characteristics, e.g. request length, update ratios, read-and-modify ratios. Experimental results show that the optimized page and block size can achieve up to 15 times better performance than the conventional NFM configuration in various applications. The results can be used to optimize the system-level objectives of a system with specific applications, e.g. embedded systems with NFM chips, or predict the future direction of NFM.

Power Failure Protection Scheme for Reliable High-Performance Solid State Disks

BANG, Kwanhu,IM, Kyung-Il,KIM, Dong-gun,PARK, Sang-Hoon,CHUNG, Eui-Young 'Institute of Electronics, Information and Communi 2013 IEICE transactions on information and systems Vol.96e.d No.5

캐시 버퍼와 읽기 요청을 고려한 낸드 플래시 기반 솔리드 스테이트 디스크의 요청 스케줄링 기법

방관후(Kwanhu Bang),박상훈(Sang-Hoon Park),이혁준(Hyuk-Jun Lee),정의영(Eui-Young Chung) 대한전자공학회 2013 전자공학회논문지 Vol.50 No.8

솔리드 스테이트 디스크 (SSD)는 고성능 개인용 컴퓨터나 서버 분야에서 뛰어난 특성과 성능을 바탕으로 입지를 넓혀 나가고 있다. 특히 낸드 플래시 메모리에 기반한 SSD가 주류를 이루며 이미 거대한 시장을 확보하고 있는 낸드 플래시 메모리 시장의 큰 부분을 차지하고 있다. 이러한 낸드 플래시 메모리 기반 SSD에는 보통 낸드 플래시 메모리의 특성을 숨기기 위하여 DRAM으로 제작되는 캐시 버퍼가 장착되는데 이 캐시 버퍼는 보다 높은 성능을 달성하기 위해 나중 쓰기 방식을 활용하고 이는 기존의 낸드 플래시 메모리 만을 고려한 스케줄링 기법들을 I/F에서 효과적으로 활용할 수 없게 한다. 따라서 본 논문에서는 I/F에서 사용할 수 있는 캐시 버퍼를 고려한 스케줄링 기법을 제안하고자 한다. 스케줄링 기법은 크게 두 가지 기준을 가지고 스케줄링을 진행하는데 캐시 버퍼의 적중 여부와 읽기 요청에 대한 우선순위이다. 이는 캐시 버퍼에 적중한 요청들을 먼저 처리하여 처리속도를 증가시키고 시스템 성능에 보다 큰 영향을 끼치는 읽기 요청의 지연시간을 줄이기 위함이다. 실험 결과에 따르면 제안하는 스케줄링 기법을 사용했을 때 약 26% 향상된 읽기 성능을 보여주었다. Solid-state disks (SSDs) have been widely used by high-performance personal computers or servers due to its good characteristics and performance. The NAND flash-based SSDs, which take large portion of the whole NAND flash market, are the major type of SSDs. They usually integrate a cache buffer which is built from DRAM and uses the write-back policy for better performance. Unfortunately, the policy makes existing scheduling methods less effective at the I/F level of SSDs Therefore, in this paper, we propose a scheduling method for the I/F with consideration of the cache buffer. The proposed method considers the hit/miss status of cache buffer and gives higher priority to the read requests. As a result, the requests whose data is hit on the cache buffer can be handled in advance and the read requests which have larger effects on the whole system performance than write requests experience shorter latency. The experimental results show that the proposed scheduling method improves read latency by 26%.

논리 블록의 접근경향을 활용한 이종 낸드 플래시 기반 저장장치를 위한 Flash Translation Layer

방관후(Kwanhu Bang),박상훈(Sang-Hoon Park),이혁준(Hyuk-Jun Lee),정의영(Eui-Young Chung) 대한전자공학회 2013 전자공학회논문지 Vol.50 No.5

낸드 플래시 메모리에 기반 한 저장장치는 이미 여러 분야에서 기존 디스크 기반 저장장치를 대체하며 거대한 규모의 시장을 확보하고 있다. 이 중 집적도는 높지만 성능과 신뢰성이 상대적으로 낮은 multi-level cell (MLC) 낸드 플래시 메모리와 반대의 특성을 지니는 single-level cell (SLC) 낸드 플래시 메모리를 혼용하여 서로의 장점만을 얻고자 하는 이종 낸드 플래시 기반 저장장치에 관한 연구 또한 활발하게 이루어지고 있다. 이종 낸드 플래시 기반 저장장치에서는 SLC에 기록된 데이터가 MLC로 옮겨질 경우에 발생하는 마이그레이션 오버헤드와, 상대적으로 적은 용량의 SLC 내부에서 발생하는 가비지 컬렉션 오버헤드가 전체 저장장치의 성능을 악화시키는 문제가 있는데, 본 논문에서는 이를 완화하고자 논리 블록의 접근경향을 활용하여 SLC를 효율적으로 활용하는 이종 낸드 플래시 기반 저장장치용 flash translation layer (FTL)을 제안하고자 한다. 제안하는 FTL 은 논리 블록들의 접근 경향을 파악하여 SLC에 기록되었을 시 성능 향상을 가져올 것이라고 기대되는 논리 블록들만을 선별하여 SLC에 기록하게 된다. 실험 결과 본 논문에서 제안하는 FTL을 사용한 이종 낸드 플래시 기반 저장장치는 기존 FTL 대비 전체 실행 시간에서 35% 향상된 성능을 보여주었다. The market for NAND flash-based storage devices has grown significantly as they rapidly replace traditional disk-based storage devices. Heterogeneous NAND flash-based storage devices using both multi-level cell (MLC) and single-level cell (SLC) NAND flash memories are also actively researched since both types of memories complement each other. Heterogeneous NAND flash-based storage devices suffer from the overheads incurred by migration from SLC to MLC and garbage collection of SLC. This paper proposes a new flash translation layer (FTL) for heterogeneous NAND flash-based storage devices to reduce the overheads by utilizing SLC efficiently. The proposed FTL analyzes the access patterns of logical blocks and selects and stores only logical blocks expected to bring performance improvement in SLC. The experimental results show that the total execution time of heterogeneous NAND flash-based storage devices with our proposed FTL scheme is 35% shorter than that with the previously proposed best FTL scheme.

Solid-State Disk의 빠른 구조 탐색 및 최적화를 위한 상위 수준 시뮬레이션 환경

방관후(Kwanhu Bang),정의영(Eui-Young Chung) 대한전자공학회 2010 대한전자공학회 학술대회 Vol.2010 No.6

Recently, flash memory-based Solid-State Disk (SSD) is being spotlighted as a large-sized and high-performance storage device. In order to further improve the performance of SSD, it is required to explore the internal architecture of it as well as efficient algorithms for Flash Translation Layer (FTL). In this paper, we constructed a high-level SSD hardware platform using SystemC so that fast architecture exploration is possible. In addition, a variety of FTL algorithms can be evaluated quantitatively on the platform. Using our environment, both hardware and software part of SSD can be optimized fast.

Run-Time Adaptive Workload Estimation for Dynamic Voltage Scaling

Sung-Yong Bang,Kwanhu Bang,Sungroh Yoon,Eui-Young Chung IEEE 2009 IEEE transactions on computer-aided design of inte Vol.28 No.9

<P>Dynamic voltage scaling (DVS) is a popular energy-saving technique for real-time tasks. The effectiveness of DVS critically depends on the accuracy of workload estimation, since DVS exploits the slack or the difference between the deadline and execution time. Many existing DVS techniques are profile based and simply utilize the worst-case or average execution time without estimation. Several recent approaches recognize the importance of workload estimation and adopt statistical estimation techniques. However, these approaches still require extensive profiling to extract reliable workload statistics and furthermore cannot effectively handle time-varying workloads. Feedback-control-based adaptive algorithms have been proposed to handle such nonstationary workloads, but their results are often too sensitive to parameter selection. To overcome these limitations of existing approaches, we propose a novel workload estimation technique for DVS. This technique is based on the Kalman filter and can estimate the processing time of workloads in a robust and accurate manner by adaptively calibrating estimation error by feedback. We tested the proposed method with workloads of various characteristics extracted from eight MPEG video clips. To thoroughly evaluate the performance of our approach, we used both a cycle-accurate simulator and an XScale-based test board. Our simulation result demonstrates that the proposed technique outperforms the compared alternatives with respect to the ability to meet given timing and Quality of Service constraints. Furthermore, we found that the accuracy of our approach is almost comparable to the oracle accuracy achievable only by offline analysis. Experimental results indicate that using our approach can reduce energy consumption by 57.5% on average, only with negligible deadline miss ratio (DMR) around 6.1%. Moreover, the average of computational overheads for the proposed technique is just 0.3%, which is the minimum value compared to other methods. More importantly, the DMR of our method is bounded by 11.7% in the worst case, while those of other methods are twice or more than ours.</P>

Solid-State Disk with Double Data Rate DRAM Interface for High-Performance PCs

KIM, Dong,BANG, Kwanhu,HA, Seung-Hwan,PARK, Chanik,CHUNG, Sung Woo,CHUNG, Eui-Young The Institute of Electronics, Information and Comm 2009 IEICE transactions on information and systems Vol.92 No.4

<P>We propose a Solid-State Disk (SSD) with a Double Data Rate (DDR) DRAM interface for high-performance PCs. Traditional SSDs simply inherit the interface protocol of Hard Disk Drives (HDD) such as Parallel Advanced Technology Attachment (PATA) or Serial-ATA (SATA) for maintaining the compatibility. However, SSD itself provides much higher performance than HDD, hence the interface also needs to be enhanced. Unlike the traditional SSDs, the proposed SSD with DDR DRAM interface is placed in the North Bridge which provides two or more DDR DRAM interface ports in high-performance PCs. The novelty of our work is on DQS signaling scheme which allows arbitrary Column Address Strobe (CAS) latency unlike typical DDR DRAM interface scheme. The experimental results show that the proposed SSD maximally outperforms the traditional SSD by 8.7 times in read mode, by 1.5 times in write mode. Also, for synthetic workloads, the proposed scheme shows performance improvement over the conventional architecture by a factor of 1.6 times.</P>

Architecture Exploration of High-Performance PCs with a Solid-State Disk

Kim, Dong,Bang, Kwanhu,Ha, Seung-Hwan,Yoon, Sungroh,Chung, Eui-Young IEEE 2010 IEEE Transactions on Computers Vol.59 No.7

<P>As the cost per bit of NAND flash memory devices rapidly decreases, NAND-flash-based Solid-State Disks (SSDs) are replacing Hard Disk Drives (HDDs) used in a wide spectrum of consumer computing devices. Although typical SSDs can deliver higher performances than HDDs can, the full capabilities of SSDs are currently not exploited in most systems. This is because an SSD is interfaced with its host system using the architectures and interface protocols designed for HDDs, due to compatibility issues. Given the pace at which the stand-alone performance of SSDs improves, the performance loss of SSDs due to the legacy interface and system architecture will soon become intolerable. To address this issue, we propose several architectural choices to fully exploit the performance of SSDs used in consumer PC architectures. More specifically, we explore its interface scheme, and data transfer concurrency with the change of the conventional PC architecture if necessary. We evaluated the performance of the architectural choices by prototyping them with SystemC. The experimental results guide us how to trade off the performance enhancement and the change of the PC architecture. The performance improvement was maximized by 2.67 times when the PC architecture is changed to support a dual-port SSD connected to the North Bridge via the Double-Data Rate (DDR) interface in real trace environments.</P>