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Multi-channel 5Gb/s/ch SERDES with Emphasis on Integrated Novel Clocking Strategies
Zhang, Changchun,Li, Ming,Wang, Zhigong,Yin, Kuiying,Deng, Qing,Guo, Yufeng,Cao, Zhengjun,Liu, Leilei The Institute of Electronics and Information Engin 2013 Journal of semiconductor technology and science Vol.13 No.4
Two novel clocking strategies for a high-speed multi-channel serializer-deserializer (SERDES) are proposed in this paper. Both of the clocking strategies are based on groups, which facilitate flexibility and expansibility of the SERDES. One clocking strategy is applicable to moderate parallel I/O cases, such as high density, short distance, consistent media, high temperature variation, which is used for the serializer array. Each group within the strategy consists of a full-rate phase-locked loop (PLL), a full-rate delay-locked loop (DLL), and two fixed phase alignment (FPA) techniques. The other is applicable to more awful I/O cases such as higher speed, longer distance, inconsistent media, serious crosstalk, which is used for the deserializer array. Each group within the strategy is composed of a PLL and two DLLs. Moreover, a half-rate version is chosen to realize the desired function of 1:2 deserializer. Based on the proposed clocking strategies, two representative ICs for each group of SERDES are designed and fabricated in a standard $0.18{\mu}m$ CMOS technology. Measurement results indicate that the two SERDES ICs can work properly accompanied with their corresponding clocking strategies.
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Multi-channel 5Gb/s/ch SERDES with Emphasis on Integrated Novel Clocking Strategies
Changchun Zhang,Ming Li,Zhigong Wang,Kuiying Yin,Qing Deng,Yufeng Guo,Zhengjun Cao,Leilei Liu 대한전자공학회 2013 Journal of semiconductor technology and science Vol.13 No.4
Two novel clocking strategies for a high-speed multi-channel serializer-deserializer (SERDES) are proposed in this paper. Both of the clocking strategies are based on groups, which facilitate flexibility and expansibility of the SERDES. One clocking strategy is applicable to moderate parallel I/O cases, such as high density, short distance, consistent media, high temperature variation, which is used for the serializer array. Each group within the strategy consists of full-rate phase-locked loop (PLL), a full-rate delay-locked loop (DLL), and t재 fixed phase alignment (FPA) techniques. The other is applicable to more awful I/O cases such as higher speed, longer distance, inconsistent media, serious crosstalk, which is used for the deserializer array. Each group within the strategy is composed of a PLL and two DLLs. Moreover, a half-rate version is chosen to realize the desired function of 1:2 deserializer. Based on the proposed clocking strategies, two representative ICs for each group of SERDES are designed and fabricated in a standard 0.18㎛ CMOS technology. Measurement results indicate that the two SERDES ICs can work properly accompanied with their corresponding clocking strategies.
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