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Improved Mold Level Control for Continuous Steel Casting by Fuzzy Logic Control
Kueon, Yeongseob,Xiao, Wendong Institute of Control 1999 Transaction on control, automation and systems eng Vol.1 No.1
This paper gives a simulation study of a new fuzzy logic control(FLC) approach for the mold level control in continuous casting processes. The proposed FLC is PID type hybridizing the conventional fuzzy PI control and Fuzzy PD control with a simplified design scheme. It is shown that, compared with the conventional control, this new control strategy can achieve superior performance for steady-state response and is more robust against process parameter variations and disturbances.
The Potential for Material Processing by Microwave Energy
Yeongseob Kueon 제어로봇시스템학회 2008 제어로봇시스템학회 국제학술대회 논문집 Vol.2008 No.10
This paper presents the potential applications for material processing by microwave energy which is electromagnetic waves that penetrates material and cause its molecules to rotate and generate heat. In this paper, potential uses of microwave energy in iron and steel making processes will be discussed in detail. Actually, microwave energy has been in use for various applications for over half century. One of the most well known applications is drying and cooking of food. Currently, industrial uses of microwave energy include direct-reduced iron making, wood processing, sintering, coke making, and so on. And moreover, CO2 and CH4 can be decomposed by super heating effect of microwave energy which can also be called as high temperature plasma furnace. In conventional heating processes, the material’ surface is heated first and then the heat moves inward, while the material is heated the entire volume at about the same time, in microwave heating processes. Microwave heating method can be used in addition to conventional heating techniques to enhance the reaction of the material processing.
D/A 변환기 INL특성을 개선시키기 위한 디글리칭 회로의 설계
권용복(Yong-Bok Kueon) 산업기술교육훈련학회 2010 산업기술연구논문지 (JITR) Vol.15 No.3
This paper describes a design of a deglitching circuit to improve integral non-linearities(INL)that is proposed. A new switching scheme for the current cell matrix of the DAC simultaneously reduces graded and symmetrical errors to improve integral non-linearities(INL). The proposed INL is designed to be operate at any supply voltage between 3V and 5V, and minimizes the glitch energy of analog outputs with deglitching circuits developed in this work. The prototype INL was implemented in a MAX 0.8um n-well single-poly double-metal CMOS technology. Experimental results show that the differential and integral non-linearities are less than ±0.5 LSB and ±0.8 LSB respectively. The ADC dissipates 75㎽ at a 3V single power supply.
듀얼-타입 전류 셀 매트릭스구조에서 CMOS D/A변환기의 설계
권용복(Yong-Bok Kueon) 산업기술교육훈련학회 2012 산업기술연구논문지 (JITR) Vol.17 No.4
This paper describes a 3.3(V) 8 bit CMOS digital to analog converter (DAC) in dual-type current cell matrix architecture which consists of a 4 MSB and a 4 LSB current matrix stage. The symmetric dual-type current cell matrix architecture allows the designed DAC to reduce not only a complexity of decoding logics, but also a number of wide swing cascade current mirrors. The designed DAC with an active chip area of 0.8(mm2)is fabricated by a 0.8(??) CMOS n-well standard analog process. The experimental data shows that the rise/fall time, the settling time, and INL/DNL are 6(ns), 15(ns) and a less than ±0.8 ±??0.75 LSB, respectively. The designed DAC is fully operational for the power supply down to 2.2(V), such that the DAC is suitable for a low voltage and a low power system application. The power dissipation of the DAC with a single power supply of 3.3(V) is measured to be 34.5(㎽).
전류 셀 매트릭스구조에서 전류구동 저 전력 10-비트 CMOS D/A변환기의 설계
권용복(Yong-Bok Kueon) 산업기술교육훈련학회 2012 산업기술연구논문지 (JITR) Vol.17 No.4
In this paper, a highly linear and low glitch 10-bit CMOS current mode digital-to-analog converter(DAC) by low-power current driving is proposed. The architecture of the DAC is based on a current steering 6+4 segmented type and new switching scheme for the current cell matrix, which reduced npn-linearity errorand graded error. In order to achieve a high performance DAC, novel current cell with a low spurious deglitching circuit and a new inverse thermometer decoder are proposed. The prototype DAC was implemented in a 0.35?? n-well CMOS technology. Experimental result show that SFDR is 60dB when sampling frequency is 32MHz and DAC output frequency is 7.92MHz. The DAC dissipates 46mW at a 3.3 Volt single power supply and occupies a chip area of 1350um × 750um.
권용복(Yong-Bok Kueon) 산업기술교육훈련학회 2010 산업기술연구논문지 (JITR) Vol.15 No.2
This paper presents the design of Improvements slew-rate operating amplifier parallel current subtracter. In the circuit designed for slew-rate programmability is based upon a newly proposed concept, that is a switched parallel current subtraction circuit with adaptive biasing technique. If the programmable slew rate amplifier is employed into mixed signal system, it can furnish the convenience timing control and optimized power dissipation. Simulated data showed the slew rate ranging from 4.17V/db to 20V/db, power dissipation ranging from 7.67mW to 3.87mW and the other circuit performance parameters were proven to be comparable with those of a conventional operational amplifier.