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Thermal Via Placement in 3D IC Interposer
Jaeik Chun,Jun Dong Cho 대한전자공학회 2010 ICEIC:International Conference on Electronics, Inf Vol.1 No.1
As the technology progresses, chip area and wire length continue to increase, causing increased interconnect delays and power consumption. Integrating several functional chips in 3D stack package leads to innovation of mobile devices. However, stacking of many chips in a 3D package leads to high heat dissipation which can causes time delay and heat failure. Our study of 3D IC thermal solution focuses on interposer. Interposers are adopted for connection of 3D chips and PCB and also used as thermal pass way through PCB. Interposer with dummy thermal via is applicable for advance heat dissipation. In this paper, we suggest cost effective thermal treatment model to reduce delay caused by thermal effect. We use dummy thermal via in interposer at critical hot-spot. The suggested model results in 7.7 percents of delay reduction on the average.