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RISS 인기검색어
- 검색키워드
- 저자 : Huan Minh Vo (검색결과 6 건)
- 무료
- 기관 내 무료
- 유료
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CMOS-Memristor Hybrid 4-bit Multiplier Circuit for Energy-Efficient Computing
Vo, Huan Minh,Truong, Son Ngoc,Shin, Sanghak,Min, Kyeong-Sik Institute of Korean Electrical and Electronics Eng 2014 전기전자학회논문지 Vol.18 No.2
In this paper, we propose a CMOS-memristor hybrid circuit that can perform 4-bit multiplication for future energy-efficient computing in nano-scale digital systems. The proposed CMOS-memristor hybrid circuit is based on the parallel architecture with AND and OR planes. This parallel architecture can be very useful in improving the power-delay product of the proposed circuit compared to the conventional CMOS array multiplier. Particularly, from the SPECTRE simulation of the proposed hybrid circuit with 0.13-mm CMOS devices and memristors, this proposed multiplier is estimated to have better power-delay product by 48% compared to the conventional CMOS array multiplier. In addition to this improvement in energy efficiency, this 4-bit multiplier circuit can occupy smaller area than the conventional array multiplier, because each cross-point memristor can be made only as small as $4F^2$.
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CMOS-Memristor Hybrid 4-bit Multiplier Circuit for Energy-Efficient Computing
Huan Minh Vo,Son Ngoc Truong,신상학,민경식 한국전기전자학회 2014 전기전자학회논문지 Vol.18 No.2
In this paper, we propose a CMOS-memristor hybrid circuit that can perform 4-bit multiplication for future energy-efficient computing in nano-scale digital systems. The proposed CMOS-memristor hybrid circuit is based on the parallel architecture with AND and OR planes. This parallel architecture can be very useful in improving the power-delay product of the proposed circuit compared to the conventional CMOS array multiplier. Particularly, from the SPECTRE simulation of the proposed hybrid circuit with 0.13-mm CMOS devices and memristors, this proposed multiplier is estimated to have better power-delay product by 48% compared to the conventional CMOS array multiplier. In addition to this improvement in energy efficiency, this 4-bit multiplier circuit can occupy smaller area than the conventional array multiplier, because each cross-point memristor can be made only as small as 4F2.
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Self-Power Gating Technique For Low Power Asynchronous Circuit
Mai, Kim-Ngan Thi,Vo, Huan Minh Institute of Korean Electrical and Electronics Eng 2018 전기전자학회논문지 Vol.22 No.3
In this paper, Asynchronous Self-Power Gating technique (ASPG) is used to reduce consumption power in asynchronous digital watch application. The power gating control signal is automatically generated by internal system operation characteristics instead of using replica circuit delay or four-phase handshaking protocol. Isolation cell is designed to insert it between power gating domain and normal operation domain. By using self-power gating circuit, asynchronous digital watch application consumes very low power and maintains data during sleep mode. The comparison results show the proposed ASPG technique saves leakage power up to 40.47% and delay time is reduced to 71% compared to the conventional circuit.
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Self-Power Gating Technique For Low Power Asynchronous Circuit
Kim-Ngan Thi Mai,Huan Minh Vo 한국전기전자학회 2018 전기전자학회논문지 Vol.22 No.3
In this paper, Asynchronous Self-Power Gating technique (ASPG) is used to reduce consumption power in asynchronous digital watch application. The power gating control signal is automatically generated by internal system operation characteristics instead of using replica circuit delay or four-phase handshaking protocol. Isolation cell is designed to insert it between power gating domain and normal operation domain. By using self-power gating circuit, asynchronous digital watch application consumes very low power and maintains data during sleep mode. The comparison results show the proposed ASPG technique saves leakage power up to 40.47% and delay time is reduced to 71% compared to the conventional circuit.
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Experimental Demonstration of Sequence Recognition of Serial Memristors
Son Ngoc Truong,Khoa Van Pham,양원선,조안재,Huan Minh Vo,이미정,민경식 대한금속·재료학회 2017 ELECTRONIC MATERIALS LETTERS Vol.13 No.1
The sequence recognition is very essential in mimicking brain’s neocorticalfunction because most of input patterns to brain’s neocortex are dynamicallychanging over time, not static regardless of time. In this paper, we experimentallydemonstrate the sequence recognition for various input sequences using serialmemristors, for the first time. In this experiment, the serial memristors are used,which were fabricated with carbon fiber and aluminum film on glass substrate. Toverify the sequence recognition, we store the following 3 sequences in thefabricated serial memristors, which are ‘A’→‘B’→‘C’, ‘B’→‘A’→‘C’, and‘C’→‘B’→‘A’, respectively. By performing this experiment, it is verified theserial memristors are changed to Low Resistance State only when the inputsequence matches the stored one. When the input sequence is different from thestored one, the serial memristors remain unchanged. The simple voltagecomparator can be used to sense the output voltage to indicate whether thesequence matching happens or not. This experimental demonstration can be veryuseful to realize memristor crossbars which can process the temporal andsequential patterns in future.
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Zero-Sleep-Leakage Flip-Flop Circuit With Conditional-Storing Memristor Retention Latch
Chul-Moon Jung,Kwan-Hee Jo,Eun-Sub Lee,Huan Minh Vo,Kyeong-Sik Min IEEE 2012 IEEE TRANSACTIONS ON NANOTECHNOLOGY Vol.11 No.2
<P>In this paper, two new zero-sleep-leakage flip-flop (F-F) circuits are proposed to make the sleep leakage literally zero. At the sleep-in time, the F-F's data are transferred to memristor retention latch; thus, the F-F can be completely cutoff from the external power supply saving the energy leak during the sleep time. The conditional storing circuit in the F-F (type-2) can reduce switching power by 87% in storing the data than the F-F (type-1). And, the crossover time of the F-F (type-2) is shortened by 97% than the F-F (type-1).</P>
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