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최준명,신상학,민경식,Choi, Jun-Myung,Sin, SangHak,Min, Kyeong-Sik 한국전기전자학회 2013 전기전자학회논문지 Vol.17 No.3
본 논문에서는 멤리스터 에뮬레이터 회로를 PCB 보드 상에서 구현하여 이의 측정을 통해서 멤리스터의 고유한 pinched hysteresis 특성을 관찰하였다. PCB 보드 상에서 구현된 멤리스터 에뮬레이션 회로는 간단한 부품으로 구성되어 있고 복잡한 회로 블록을 사용하지 않았기 때문에 집적회로의 구현 시에도 매우 작은 면적으로 설계가 가능하다는 장점이 있다. 또한 본 논문에서는 프로그램 가능한 이득증폭기를 멤리스터 에뮬레이션 회로를 사용하여 설계해서 이 회로의 전압이득이 멤리스터의 저항의 프로그래밍을 통해서 조절이 가능하다는 것을 보였다. 이득증폭기에 사용되는 멤리스터 에뮬레이션 회로의 구현을 위해서 멤리스터 소자의 특성 중에 하나인 threshold switching 특성이 회로로 구현되어 VREF 보다 낮은 전압이 인가되었을 때는 멤리스터의 저항 값이 변하지 않도록 설계하였고 이의 동작을 시뮬레이션을 통해서 검증하였다. 본 논문에서 PCB 보드 상에서 구현되고 검증된 멤리스터 에뮬레이션 회로와 이 회로를 이용한 프로그램 가능한 이득증폭기는 멤리스터 소자의 실제 제작이 불가능한 경우에, 멤리스터의 동작과 기능, 특성 및 멤리스터 응용회로의 이해에 많은 도움이 될 것이다. In this paper, we implemented memristor emulator circuit on Printed Circuit Board (PCB) and observed the inherent pinched hysteresis characteristic of memristors by measuring the emulator circuit on PCB. The memristor emulator circuit implemented on PCB is composed of simple discrete devices not using any complicated circuit blocks thus we can integrate the memristor emulator circuits in very small layout area on Silicon substrate. The programmable gain amplifier is designed using the proposed memristor emulator circuit and verified that the amplifier's voltage gain can be controlled by programming memristance of the emulator circuit by circuit simulation. Threshold switching is also realized in the proposed emulator circuit thus memristance can remain unchanged when the input voltage applied to the emulator circuit is lower than VREF. The memristor emulator circuit and the programmable gain amplifier using the proposed circuit can be useful in teaching the device operation, functions, characteristics, and applications of memristors to students when thet cannot access to device and fabrication technologies of real memristors.
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채윤식,채기성,윤예오,우상욱,신상학,이종수 한국정밀공학회 2018 International Journal of Precision Engineering and Vol.19 No.8
The present study included the finite element analysis and optimal design of a multi-layered foldable structure (foldable display) to satisfy stress, neutral plane, and delamination requirements under a 2.5 mm radius of curvature (i.e., 2.5R) due to static bending load. Two bending types (inner folding and outer folding) were considered to accommodate the repeated bending, and their maximum stress values were evaluated. In the approximate optimization for the thickness and Young’s modulus of multiple film layers, the objective was to minimize the folding stress subjected to constraints on the positioning of the largest stress value to a neutral plane and prevention of delamination. Through the simultaneous change in thickness and Young’s modulus, the study identified the new position of a neutral axis so that a 16% improvement in the stress magnitude was obtained. A simulation-based T-peel test was also performed to analyze the fracture behavior of the adhesive, and the relation between the fracture toughness GC and separation load LP could be expressed as Lp = 12.687Gc. The optimized objective function value of von Mises stress was improved by 18% compared to an initial design, and constraints of the delamination indicator and positioning of the neutral plane were satisfied.
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CMOS-Memristor Hybrid 4-bit Multiplier Circuit for Energy-Efficient Computing
Huan Minh Vo,Son Ngoc Truong,신상학,민경식 한국전기전자학회 2014 전기전자학회논문지 Vol.18 No.2
In this paper, we propose a CMOS-memristor hybrid circuit that can perform 4-bit multiplication for future energy-efficient computing in nano-scale digital systems. The proposed CMOS-memristor hybrid circuit is based on the parallel architecture with AND and OR planes. This parallel architecture can be very useful in improving the power-delay product of the proposed circuit compared to the conventional CMOS array multiplier. Particularly, from the SPECTRE simulation of the proposed hybrid circuit with 0.13-mm CMOS devices and memristors, this proposed multiplier is estimated to have better power-delay product by 48% compared to the conventional CMOS array multiplier. In addition to this improvement in energy efficiency, this 4-bit multiplier circuit can occupy smaller area than the conventional array multiplier, because each cross-point memristor can be made only as small as 4F2.
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