http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
- 中文 을 입력하시려면 zhongwen을 입력하시고 space를누르시면됩니다.
- 北京 을 입력하시려면 beijing을 입력하시고 space를 누르시면 됩니다.
RISS 인기검색어
- 검색키워드
- 저자 : Hoyoung Tang (검색결과 4 건)
- 무료
- 기관 내 무료
- 유료
-
쓰기 동작의 에너지 감소를 통한 비터비 디코더 전용 저전력 임베디드 SRAM 설계
당호영(Hoyoung Tang),신동엽(Dongyeob Shin),송동후(Donghoo Song),박종선(Jongsun Park) 대한전자공학회 2013 전자공학회논문지 Vol.50 No.11
비터비 디코더(Viterbi decoder)용 임베디드 SRAM은 범용(General purpose) CPU에 쓰이는 SRAM과 달리 읽기, 쓰기 동작이 비터비 복호 알고리즘에 따라 일정한 액세스 패턴을 갖고 동작한다. 이 연구를 통하여 제안된 임베디드 SRAM의 구조는 이러한 메모리 동작의 패턴에 최적화되어 워드라인과 비트라인에서 발생하는 불필요한 전력소모를 제거함으로써 쓰기 동작의 소모 전력을 크게 줄일 수 있다. 65nm CMOS 공정으로 설계된 비터비 디코더는 본 논문에서 제안된 SRAM 구조를 이용하여 기존의 임베디드 SRAM 대비 8.92%만큼 면적증가로 30.84% 소모 전력 감소를 이룩할 수 있었다. By exploiting the regular read and write access patterns of embedded SRAM memories inside Viterbi decoder, the memory architecture can be efficiently modified to reduce the power consumption of write operation. According to the experimental results with 65nm CMOS process, the proposed embedded memory used for Viterbi decoder achieves 30.84% of power savings with 8.92% of area overhead compared to the conventional embedded SRAM approaches.
-
Energy Efficient Canny Edge Detector for Advanced Mobile Vision Applications
Lee, Juseong,Tang, Hoyoung,Park, Jongsun IEEE 2018 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDE Vol.28 No.4
<P>In this paper, we present an energy-efficient architecture of the Canny edge detector for advanced mobile vision applications. Three key techniques for reducing computational complexity of the Canny edge detector are presented. First, by exploiting the rank characteristic of the convolution kernel of Gaussian smoothing and Sobel gradient filters, common computations are identified and shared in the image filter design to reduce the number of additions and multiplications. For the gradient magnitude/direction computation, only three directions of neighboring pixels are considered to reduce computation energy with minor degradation on conformance performance (CP). For the adaptive threshold selections, an interesting observation is that the mean values of gradient magnitudes show small variations depending on the classified block types. Thus, the threshold selection process can be simplified as multiplying the mean value of the local block with predecided constants. The proposed low complexity Canny edge detector has been implemented using both field-programmable gate arrays (FPGAs) and a 65-nm standard-cell library. The FPGA implementation with Xilinx Virtex-V (XC5VSX240T) shows that our edge detector achieves 48% of area and 73% of execution time savings over the conventional architecture without seriously sacrificing the detection performance. The proposed edge detector implemented with 65-nm standard-cell library can easily support real-time ultrahigh definition video data processing (50 frames/s) with the power consumption of 5.48 mW (108.84 <TEX>$\mu \text{J}$</TEX>/frame).</P>
-
An Adaptive Impedance-Matching Network Based on a Novel Capacitor Matrix for Wireless Power Transfer
Yongseok Lim,Hoyoung Tang,Seungok Lim,Jongsun Park Institute of Electrical and Electronics Engineers 2014 IEEE transactions on power electronics Vol. No.
<P>In a wireless power transfer (WPT) system via the magnetic resonant coupling, one of the most challenging design issues is to maintain a reasonable level of power transfer efficiency (PTE), even when the distance between the transmitter and the receiver changes. When the distance varies, the PTE drastically decreases due to the impedance mismatch between the resonator of the transmitter and that of the receiver. This paper presents a novel serial/parallel capacitor matrix in the transmitter, where the impedance can be automatically reconfigured to track the optimum impedance-matching point in the case of varying distances. The dynamic WPT matching system is enabled by changing the combination of serial and parallel capacitors in the capacitor matrix. An interesting observation in the proposed capacitor matrix is that the resonant frequency is not shifted, even with capacitor-matrix tuning. In order to quickly find the best capacitor combination that achieves maximum power transfer, a window-prediction-based search algorithm is also presented in this paper. The proposed resonance WPT system is implemented using a resonant frequency of 13.56 MHz, and the experimental results with 1W power transfer show that the transfer efficiency increases up to 88 % when the distance changes from 0 to 1.2 m.</P>
-
Pipelined Bitonic 정렬기 전용 저전력 임베디드 SRAM
최경락(Kyungrak Choi),정진일(Jinil Chung),당호영(Hoyoung Tang),최웅(Woong Choi),박종선(Jongsun Park) 대한전자공학회 2016 대한전자공학회 학술대회 Vol.2016 No.6
In this paper, embedded SRAM architecture for bitonic sorter is customized to reduce the unnecessary power consumption. It can be efficiently modified by analyzing the general read and write access patterns. There are some of the needless controls between read and write operations and it can be optimized. According to the simulation results with 65nm CMOS process, the proposed embedded memory used for bitonic sorter achieves 18.75% of power savings with 4.88% of overhead compared to the conventional embedded SRAM approaches.
ScienceON
DBpia연관 검색어 추천
이 검색어로 많이 본 자료
활용도 높은 자료
