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- 저자 : Hanuman C. R. S. (검색결과 1 건)
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Analysis Optimum Sizing of 12 T PCSA for High Speed Soft Error Tolerant Logic Circuits Design
Aruna A. Ranjani,Kamala J.,Hanuman C. R. S.,Vaithiyanathan Dhandapani 대한전기학회 2022 Journal of Electrical Engineering & Technology Vol.17 No.6
Recent developments in electronics aim at low power, multitasking, small size intelligent and smart appliances. Memory should be an integral part of the appliances to achieve intelligence in smart devices. Perpendicular magnetic tunnel junction (PMTJ) is a novel semiconductor device that fulfi lls the demands of modern electronics in the design of memories. They are used to provide nonvolatile inputs for the logic circuits and in-memory computing. These devices are based on either spin transfer torque (STT) or spin–orbit torque (SOT) switching mechanisms. This paper proposes an optimum sizing of 12 T pre charge sense amplifi er (PCSA). The circuit is analysed for soft error tolerance and noise analysis. It shows that it is more reliable than the SRAM and DCM-based sense amplifi er. The equal sizing is chosen for NMOS and PMOS devices, ignoring mobility considerations. A full adder (FA) and logic gate—AND are designed with magnetic writing circuit, NMOS tree and proposed 12 T PCSA. The error tolerance is analysed by inducing single event multiple upset (SEMU) at vulnerable nodes of the 12 T optimized structure. It has been proven that the SOT based read write parallel switching (RWPS) circuit integrated with the proposed PCSA has a higher error tolerance rate and speed. The SOT-based logic structures have 64% and 60% reduced delay for FA and logic AND gate, respectively, compared to STT based switching circuits. The WSNM and RSNM characteristics are analysed for 6 T and 12 T SRAM architecture. This paper designs SOT based complex hybrid magnetic/ CMOS structures with higher tolerance against radiation using optimized PCSA and it is suitable for aerospace application.
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