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RISS 인기검색어
- 검색키워드
- 저자 : Haiqing Nan (검색결과 4 건)
- 무료
- 기관 내 무료
- 유료
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Haiqing Nan,Choi, K. IEEE 2012 IEEE transactions on circuits and systems. a publi Vol.59 No.7
<P>In this paper, three high performance, low cost and robust latches (referred to as HLR, HLR-CG1, and HLR-CG2) are proposed in 45 nm CMOS technology. The proposed latches are completely insensitive to transient faults at their internal nodes and output node independent of the size and technology of the CMOS transistor. The proposed latches tolerate transient faults regardless of the energy of the striking particle. The proposed latches offer faster speed, higher reliability to transient faults with lower costs regarding power and area than most of the latches recently proposed in the literature. The proposed designs demonstrate that the power-delay-product benefit is 13 times on average compared to previous robust latches including standard latch.</P>
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Nan, Haiqing,Kim, Kyung-Ki,Wang, Wei,Choi, Ken Korea Information Processing Society 2011 Journal of information processing systems Vol.7 No.1
In deeply scaled CMOS technologies, two major non-ideal factors are threatening the survival of the CMOS; i) PVT (process, voltage, and temperature) variations and ii) leakage power consumption. In this paper, we propose a novel post-silicon tuning methodology to scale optimum voltage and frequency "dynamically". The proposed design technique will use our PVT sensor circuits to monitor the variations and based on the monitored variation data, voltage and frequency will be compensated "automatically". During the compensation process, supply voltage is dynamically adjusted to guarantee the minimum total power consumption without violating the frequency requirement. The simulation results show that the proposed technique can reduce the total power by 85% and the static power by 53% on average for the selected ISCAS'85 benchmark circuits with 45 nm CMOS technology compared to the results of the traditional PVT compensation method.
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TDDB Monitoring and Compensation Circuit Design for Deeply Scaled CMOS Technology
Haiqing Nan,Kyuwon Choi IEEE 2013 IEEE transactions on device and materials reliabil Vol.13 No.1
<P>In this paper, a time-dependent dielectric breakdown (TDDB) compensation method with two TDDB monitoring circuits for reliable designs is proposed in 32-nm CMOS technology. To the best of our knowledge, there is no TDDB compensation method or TDDB monitoring circuits proposed before. The proposed TDDB monitoring circuits are referred to as soft breakdown (SBD) monitoring circuit and hard breakdown (HBD) monitoring circuit, which generate a fixed output pattern when severe SBD or HBD occurs. Based on the output of the monitoring circuits, the TDDB compensation method is proposed to completely overcome severe performance degradation and functionality failure due to SBD and HBD. The effectiveness and design costs of the proposed designs are evaluated using ISCAS'85 benchmark circuits.</P>
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Activity-Driven Fine-Grained Clock Gating and Run Time Power Gating Integration
Li Li,Ken Choi,Haiqing Nan IEEE 2013 IEEE transactions on very large scale integration Vol.21 No.8
<P>As the two most widely used techniques to reduce dynamic power and leakage power, clock gating (CG) and power gating (PG), respectively, are expected to be integrated together effectively. Normally, the implementation of CG leads to some redundant operations, which provides the opportunity to apply PG. In this brief, we have proposed an activity-driven fine-grained CG and PG integration. First, we introduce an optimized bus-specific-clock-gating (OBSC) scheme to improve traditional XOR-based CG. It chooses only a subset of flip-flops (FFs) to be gated selectively, and the problem of gated FF selection is reduced from exponential complexity into linear. Then those combinational logics, which completely depend on the outputs of gated FFs, are performing redundant operations. They can be power gated, and the clock enable signal generated by OBSC is used as the sleep signal. A minimum average idle time concept is proposed to determine whether the insertion of PG will lead to energy reduction. In order to evaluate our technique, we experimented on twenty ISCAS'89 circuits. The simulation results show that 25.07% dynamic power can be reduced by OBSC, and 50.19% active leakage power can be saved by PG.</P>
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