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RISS 인기검색어
- 검색키워드
- 저자 : Guduri, Manisha (검색결과 2 건)
- 무료
- 기관 내 무료
- 유료
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Novel Pass-transistor Logic based Ultralow Power Variation Resilient CMOS Full Adder
Guduri, Manisha,Islam, Aminul The Institute of Electronics and Information Engin 2017 Journal of semiconductor technology and science Vol.17 No.2
This paper proposes a new full adder design based on pass-transistor logic that offers ultra-low power dissipation and superior variability together with low transistor count. The pass-transistor logic allows device count reduction through direct logic realization, and thus leads to reduction in the node capacitances as well as short-circuit currents due to the absence of supply rails. Optimum transistor sizing alleviates the adverse effects of process variations on performance metrics. The design is subjected to a comparative analysis against existing designs based on Monte Carlo simulations in a SPICE environment, using the 22-nm CMOS Predictive Technology Model (PTM). The proposed ULP adder offers 38% improvement in power in comparison to the best performing conventional designs. The trade-off in delay to achieve this power saving is estimated through the power-delay product (PDP), which is found to be competitive to conventional values. It also offers upto 79% improvement in variability in comparison to conventional designs, and provides suitable scalability in supply voltage to meet future demands of energy-efficiency in portable applications.
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Novel Pass-transistor Logic based Ultralow Power Variation Resilient CMOS Full Adder
Manisha Guduri,Aminul Islam 대한전자공학회 2017 Journal of semiconductor technology and science Vol.17 No.2
This paper proposes a new full adder design based on pass-transistor logic that offers ultralow power dissipation and superior variability together with low transistor count. The pass-transistor logic allows device count reduction through direct logic realization, and thus leads to reduction in the node capacitances as well as short-circuit currents due to the absence of supply rails. Optimum transistor sizing alleviates the adverse effects of process variations on performance metrics. The design is subjected to a comparative analysis against existing designs based on Monte Carlo simulations in a SPICE environment, using the 22-nm CMOS Predictive Technology Model (PTM). The proposed ULP adder offers 38% improvement in power in comparison to the best performing conventional designs. The trade-off in delay to achieve this power saving is estimated through the power-delay product (PDP), which is found to be competitive to conventional values. It also offers upto 79% improvement in variability in comparison to conventional designs, and provides suitable scalability in supply voltage to meet future demands of energy-efficiency in portable applications.
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