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Wang, Chuan,Chien, Jun-Chau,Fang, Hui,Takei, Kuniharu,Nah, Junghyo,Plis, E.,Krishna, Sanjay,Niknejad, Ali M.,Javey, Ali American Chemical Society 2012 Nano letters Vol.12 No.8
<P>This paper reports the radio frequency (RF) performance of InAs nanomembrane transistors on both mechanically rigid and flexible substrates. We have employed a self-aligned device architecture by using a T-shaped gate structure to fabricate high performance InAs metal-oxide-semiconductor field-effect transistors (MOSFETs) with channel lengths down to 75 nm. RF measurements reveal that the InAs devices made on a silicon substrate exhibit a cutoff frequency (<I>f</I><SUB>t</SUB>) of ∼165 GHz, which is one of the best results achieved in III–V MOSFETs on silicon. Similarly, the devices fabricated on a bendable polyimide substrate provide a <I>f</I><SUB>t</SUB> of ∼105 GHz, representing the best performance achieved for transistors fabricated directly on mechanically flexible substrates. The results demonstrate the potential of III–V-on-insulator platform for extremely high-frequency (EHF) electronics on both conventional silicon and flexible substrates.</P><P><B>Graphic Abstract</B> <IMG SRC='http://pubs.acs.org/appl/literatum/publisher/achs/journals/content/nalefd/2012/nalefd.2012.12.issue-8/nl301699k/production/images/medium/nl-2012-01699k_0001.gif'></P><P><A href='http://pubs.acs.org/doi/suppl/10.1021/nl301699k'>ACS Electronic Supporting Info</A></P>
III–V Complementary Metal–Oxide–Semiconductor Electronics on Silicon Substrates
Nah, Junghyo,Fang, Hui,Wang, Chuan,Takei, Kuniharu,Lee, Min Hyung,Plis, E.,Krishna, Sanjay,Javey, Ali American Chemical Society 2012 Nano letters Vol.12 No.7
<P>One of the major challenges in further advancement of III–V electronics is to integrate high mobility complementary transistors on the same substrate. The difficulty is due to the large lattice mismatch of the optimal <I>p</I>- and <I>n</I>-type III–V semiconductors. In this work, we employ a two-step epitaxial layer transfer process for the heterogeneous assembly of ultrathin membranes of III–V compound semiconductors on Si/SiO<SUB>2</SUB> substrates. In this III–V-on-insulator (XOI) concept, ultrathin-body InAs (thickness, 13 nm) and InGaSb (thickness, 7 nm) layers are used for enhancement-mode <I>n</I>- and <I>p</I>- MOSFETs, respectively. The peak effective mobilities of the complementary devices are ∼1190 and ∼370 cm<SUP>2</SUP>/(V s) for electrons and holes, respectively, both of which are higher than the state-of-the-art Si MOSFETs. We demonstrate the first proof-of-concept III–V CMOS logic operation by fabricating NOT and NAND gates, highlighting the utility of the XOI platform.</P><P><B>Graphic Abstract</B> <IMG SRC='http://pubs.acs.org/appl/literatum/publisher/achs/journals/content/nalefd/2012/nalefd.2012.12.issue-7/nl301254z/production/images/medium/nl-2012-01254z_0002.gif'></P>