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An Effective Self-test Scheduling for Realtime Processor based System
. V. N. Ramesh,B. Naresh Kumar Reddy,V. V. Murali Krishna,B. M. Kumar Gandhi,V. Shiva,M. Dronika Devi 보안공학연구지원센터 2015 International Journal of Smart Home Vol.9 No.3
Now a days Jobs are Scheduled in a single processor or more than one processor, a real time job is scheduled or executed based on requirements, An Successful task in embedded system ought to have constrained asset necessities: Memory, execution time and power utilization, these necessity are not generally simple to fulfil in real-time embedded system with hard task deadlines. In this paper we explore the effective time utilization, without influencing the deadline requirements of typical hard real time task ,there are no limitation on the new results each task can be periodic or sporadic ,with relative deadline which can be less than ,equivalent to or greater than its period, it is too fast , best-effort ,effective real time scheduling algorithm for a wide variety of job parameters.
K. Sarangam,Aruru Sai Kumar,B. Naresh Kumar Reddy 한국전기전자재료학회 2024 Transactions on Electrical and Electronic Material Vol.25 No.2
A low-power, high-speed two-stage dynamic latch comparator suitable for high-resolution analog-to-digital converters (ADCs) is described and implemented in this work using 22 nm FinFET technology. The purpose of this research is to apply the FinFET device in low-power, high-speed analogue and mixed-signal circuits. Today, in the sub-50 nm realm, FinFETs outperform planar MOSFETs in terms of performance. In addition to a high voltage gain, other benefi ts include better channel control, reduced short-channel eff ects, low leakage current at the output, and a low output conductance. The suggested dynamic latched comparator makes use of both CMOS and FinFET technology components. By studying the device properties, the analogue performance metrics of FinFET are compared to bulk CMOS. Most dynamic comparators are able to function at fast speeds for input referred noise levels that are suffi ciently high. This is because high-resolution ADCs do not benefi t from the pre-amplifi er's limited gain. This shortcoming is addressed by way of a pre-amplifi er based on a cascode structure. The proposed comparator architectures improve the pre- amplifi er diff erential gain and minimize input referred noise. In addition, a tranconductance enhanced latch stage is used. Using 0.8 V as a supply voltage and 1 GHz clock frequency, the suggested comparator has a delay as low as 50.42 ps, input referred noise of 190 μv and an input off set voltage of 5.2 mV with a power consumption of 7.67 μW and with a low power delay product (PDP) of 0.382 fJ. The FinFET based dynamic latch comparator has 20.6%, of delay and 12.5% power dissipation improvement than bulk CMOS based dynamic latch comparator and also better PDP than conventional double tail pre-amplifi er based dynamic comparators. The proposed circuit's active area is 5.93 μm × 2.85 μm.