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Refresh 회로 구현에 따른 2T DRAM-based PIM Chip 면적 분석
최희재(Hui-Jae Choi),심원보(Wonbo Shim) 대한전자공학회 2023 대한전자공학회 학술대회 Vol.2023 No.6
The emergence of AI-based conversational services has led to a focus on the high performance semiconductor market. Technology for processing large amounts of data is essential, and to process such data, it is necessary to address the data bottleneck and power consumption increase issues in the von Neumann architecture. Processing-in-memory (PIM) acts as a key solution to these bottleneck and power consumption. In this paper, we added a refresh circuit to implement 2T DRAM in the synaptic array of the PIM chip. As a result, we analyzed the synaptic array area and the PIM chip area with the addition of the refresh circuit, and finally presented research directions for the optimal PIM chip design that can have advantages in terms of density.