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SoC Platform을 이용한 고성능 JPEG IP 구현 및 검증
김준호(Joon-ho Kim),천동엽(Dong-yeoh Chun),장호영(Ho-young Chang),이선영(Seonyoung Lee),조경순(Kyeongsoon Cho) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
This paper presents an architecture of high-performance JPEG CODEC circuit that can process one pixel per cycle. We reduced the circuit size by using a single transpose buffer and two-stage pipeline for DCT. Further reduction was achieved by sharing the buffers for VLC and VLD. Our circuit was verified using SoC platform board with Xilinx FPGA and ARM9 processor. The synthesized circuit has 48,738 gates and operates at a maximum frequency of 127㎒.