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실리콘 내부에 있는 slow trap에 의한 TAT 전류 변화 분석
고결(Kyul Ko),유성원(Sung-Won Yoo),이현슬(Hyunseul Lee),서영수(Youngsoo Seo),전상빈(Sangbin Jeon),고형우(Hyungwoo Ko),전현옥(Jeon-Hyun Ok),신형철(Hyungcheol Shin) 대한전자공학회 2015 대한전자공학회 학술대회 Vol.2015 No.6
In this paper, we present an analysis of the trap-assisted tunneling (TAT) area on gate-induced drain leakage (GIDL) current variation by the slow trap in silicon using an analytical equations. And, TAT current variation is compared with the type of charge carrier. Finally, we compared TAT GIDL current variation by slow trap in oxide with silicon region depending on the perpendicular distance of the slow trap from the interface and temperature.