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제3-고조파를 이용한 저항과 용량형 센서 인터페이스 회로 설계
사의환(Yui-Hwan Sa),손표훈(Pyo-Hoon Son),김기홍(Ki-Hong Kim),김희석(Hi-Seok Kim),차형우(Hyeong-Woo Cha) 대한전자공학회 2016 대한전자공학회 학술대회 Vol.2016 No.11
A novel resistive and capacitive interface circuit using third harmonic frequency was designed. The interface consists of fixed and variable pulse-wave oscillators, two band-pass filters with third harmonic center frequency of the two oscillators, a multiplier, and a low-pass filter(LPF). The band-pass filter outs three times capacitive(resistive) -difference frequency of the fixed and variable capacitor(resistor). The difference frequency of the multiplier was filtered by LPF and than final frequency of the LPF was proportioned to the three time of capacitive (resistive)-difference. The experimentation results show that the proposed interface has resolution of 1.59Hz/fF and nonlinearity error of 1.86%.
이중적분 방식을 이용한 새로운 용량변화-디지털 변환기 설계
김기홍(Ki-Hong Kim),손표훈(Pyo-Hoon Son),김희석(Hi-Seok Kim),차형우(Hyeong-Woo Cha) 대한전자공학회 2017 대한전자공학회 학술대회 Vol.2017 No.6
A new capacitive variation to digital(time) con-verter using dual-slope analog to digital conversion method was proposed. The converter consist of linear operational transconductance amplifer(LOTA), a reference capacitor, a sensor capacitor, a comparator, switches, and switch control logic circuit. Operation principle was similar to dual-slope A/D conversion method which has non inversion integration operation using LOTA and sum of reference and sensor capacitor, inversion integration operation using the reference capacitor, and reset operation by switch control. The simulation results shows that the proposed capacitance variation to digital converter has resolution of 18-bit and conversion time of 80msec at clock frequency of 10MHz. The supply voltage was 5V and power consumption was 2mW