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Pipeline Subranging 아날로그 - 디지탈 변환기에 관한 연구
김종대,차균현,조현묵,백경갑,백인천 고려대학교 공학기술연구소 1992 고려대학교 생산기술연구소 생기연논문집 Vol.28 No.1
In this thesis, the design of high speed pipeline subranging A/D converter is presented. The A/D converter has the subranging structure in which the 8 bits are partitioned into higher 4 bits and lower 4 bits. The pipeline method is utilized to maintain the conversion speed as fast as that of flash structure. The error correction circuit is added to detect and correct the errors within ±8 LSB error range that may be generated in the 1st comparator. The converter has been designed using a double metal 1.5 ㎛ BiCMOS technology of Samsung Electronics Co. The performance of designed converter was evaluated by using AWB(Analog Work Branch) and SPICE simulator. Results shows a conversion speed of higher than 20 ㎒ and dissipates 390 ㎽ with 5 V single power supply. Its differential nonlinearity error (DNL) is below 1 LSB and integrator nonlinearity error (INL) is below 3.2 LSB for ±2 LSB error detection range and below 2.4 LSB for ±4 LSB error detection range.