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박희천(Heechun Park),김태환(Taewhan Kim) 대한전자공학회 2015 대한전자공학회 학술대회 Vol.2015 No.11
Existing synchronous-style circuits are faced with the limit of improvement because of the malfunction from clock skew and the necessity of clock margin. To cope with those barriers, asynchronous-style circuit design is arisen again. Although asynchronous circuit is far less effective than synchronous in the past because of limitations in fabrication process, it is becoming competitive under the necessity of faster and more power-saving chips. In this paper, we compared and analyzed two typical asynchronous circuit structures, single-rail and dual rail, in the point of circuit power and area, and suggested directions of future works for designing effective asynchronous circuits.